EP610ILC10 vs EP610IDC-10 Comparison
Detailed side-by-side comparison of EP610ILC10 by Intel and EP610IDC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610ILC10 | EP610IDC-10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.10 | $8.85 |
| Family | Classic EPLD (EP610) | β |
| Logic Elements | 16 macrocells | β |
| Gates | 300 gates equivalent | β |
| Product Terms | 160 | β |
| I/O Lines | 16 | β |
| Dedicated Inputs | 4 | 4 |
| Propagation Delay (tPD) | 15 ns (10 ns speed grade) | β |
| Maximum Internal Frequency | 100 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (nominal) |
| Operating Temperature | -40 C to +85 C (Industrial) | β |
| Technology | CMOS, UV-erasable / OTP | CMOS, UV-erasable (windowed ceramic) |
| Architecture | PAL-type AND-OR-NOT | β |
| Package | 28-pin PLCC (J-Lead) | β |
| Mounting Type | Surface Mount / Socket | Through-hole |
| RoHS Status | Unknown - verify with manufacturer | [DATA_NEEDED: RoHS status of CDIP-10 variant] |
| Device Family | β | Altera Classic EPLD |
| Logic Capacity | β | 300 usable gates |
| Macrocell Count | β | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | β | 10 ns |
| Maximum Counter Frequency (fCNT) | β | 100 MHz |
| I/O Logic Compatibility | β | 100% TTL emulation |
| Package Type | β | 24-pin Ceramic DIP (CDIP) |
| I/O Pins | β | 20 |
| Operating Temperature Range | β | 0 Β°C to +70 Β°C (commercial) |
| Programmable Interconnect | β | Yes (on-chip) |
| In-System Programmability | β | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | β | Yes (per device documentation) |