EP610IPC-10 vs EP610DC-20 Comparison
Detailed side-by-side comparison of EP610IPC-10 by Altera and EP610DC-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IPC-10 | EP610DC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $15.85 |
| Family | Altera Classic EPLD | Classic EP610 |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Programmable Gates | 300 usable gates | β |
| Macrocells | 16 | β |
| Maximum Operating Frequency | 100 MHz | β |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | 22 ns |
| Product Terms | 160 total | β |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 | 16 (bidirectional) |
| Total Input Pins | 20 | β |
| Supply Voltage | 5 V | β |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | β |
| Technology | CMOS EPROM (UV-erasable / OTP) | β |
| Package | 24-pin PDIP (Plastic DIP) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Operating Temperature | -40C to +85C (industrial) | 0 Β°C to 70 Β°C (commercial) |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | UV erasure + parallel programmer |
| TTL Emulation | 100% TTL compatible | β |
| Product Type | β | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Logic Macrocells | β | 16 |
| Total Usable Pins | β | 20 |
| Product Terms (p-terms) | β | 160 |
| Maximum Toggle Frequency (fMAX) | β | 55.6 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | β | CMOS, UV-erasable floating gate |
| Mounting Type | β | Through-hole |
| RoHS Status | β | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |