EP610IPC-10 - Classic EPLD 16-Macrocell 10ns OTP PLD | Altera
MPN: EP610IPC-10 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.8 | $2,180.00 |
| 500 | $18.95 | $9,475.00 |
| 1,000 | $16.4 | $16,400.00 |
EP610IPC-10 Overview
What is a Classic EPLD? An Erasable Programmable Logic Device (EPLD) is a CMOS-based programmable logic IC that combines PAL/GAL-style AND/OR arrays with a configurable output macrocell. EPLDs sit between simple PLDs (PALs/GALs, typically tens of gates) and complex PLDs (CPLDs/FPGAs, thousands of gates). Classic EPLDs from Altera pioneered the integration of multiple PAL-equivalent functions plus buried registers into a single 24- or 28-pin DIP, allowing engineers to replace four to six discrete 20-pin PALs with one part. The EP610 is the smallest Classic family member with 16 macrocells; its siblings EP910 (24 macrocells) and EP1810 (48 macrocells) extend the architecture for larger designs.
Key features include 16 macrocells, 16 dedicated input pins (4 dedicated inputs plus 12 I/O), 20 total input pins, 160 product terms, a Turbo-only AND-OR-NOT architecture, JTAG-free ISP (programmed via an Altera Master Programming Unit or compatible third-party programmer), and 5 V CMOS/TTL-compatible I/O. Per the Classic EPLD datasheet, the device supports 100% TTL emulation and integrates cleanly with standard 74LS/74F logic families. The 24-pin PDIP form factor is friendly to through-hole prototyping and legacy system retrofits.
From a technical-depth perspective, the EP610 uses a CMOS EEPROM/UV-EPROM cell technology with a programmable interconnect array feeding a sum-of-products logic matrix. Each macrocell contains a flip-flop, output enable polarity, and feedback path to the AND array, allowing D/T/JK flip-flop and combinatorial outputs to coexist in the same device. The I pin suffix denotes the industrial operating temperature range (-40C to +85C) and ceramic-windowed (UV-erasable) package, while the C suffix indicates plastic OTP. The -10 suffix indicates the 10 ns commercial tPD grade.
Typical applications include bus-interface bridging (e.g., replacing multiple 74LS245/74LS373 glue-logic chips with one EP610), state-machine controllers in industrial automation, address decoding and wait-state generation in 80C186/68k/MIPS embedded systems, and legacy telecom backplane glue-logic. The 24-pin PDIP package is particularly valued in long-lifecycle industrial, military, and aerospace systems that prefer through-hole components for field-serviceability.
When designing with the EP610IPC-10, plan for programming infrastructure: the part requires either a UV eraser window (I grade) or one-time-programmable configuration (C grade, no window), plus an Altera-compatible device programmer. Engineers migrating new designs should also evaluate the MAX II or MAX V CPLD families as modern, in-system-programmable alternatives with longer supply continuity.
This page synthesizes current distributor availability, parametric-equivalent drop-in alternatives, and design notes not found in the original Classic EPLD datasheet, helping engineers source, second-source, and qualify the EP610IPC-10 for both new designs and legacy field-replacements.
Drop-in alternatives for EP610IPC-10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610IPC-10 (same form factor and footprint) — differing in Operating Temperature, Package, Family, Propagation Delay (tPD), Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610DC-10
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.95 / Unit
View Datasheet →EP610DC-15
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.95 / Unit
View Datasheet →EP610DI-10
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP610DC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.95 / Unit
View Datasheet →EP610DM-35
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$23.4 / Unit
View Datasheet →EP610DC-20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$15.85 / Unit
View Datasheet →EP610IPC-10 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Programmable Gates | 300 usable gates |
| Macrocells | 16 |
| Maximum Operating Frequency | 100 MHz |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) |
| Product Terms | 160 total |
| Dedicated Inputs | 4 |
| I/O Pins | 16 |
| Total Input Pins | 20 |
| Supply Voltage | 5 V |
| Architecture | Turbo-only AND-OR-NOT, PAL-type |
| Technology | CMOS EPROM (UV-erasable / OTP) |
| Package | 24-pin PDIP (Plastic DIP) |
| Operating Temperature | -40C to +85C (industrial) |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) |
| TTL Emulation | 100% TTL compatible |
EP610IPC-10 Pin Configuration
| Pin 1 | I20 / I/O — Input or bidirectional I/O pin 20 (macrocell-controlled) |
| Pin 2 | I19 / I/O — Input or bidirectional I/O pin 19 |
| Pin 3 | I18 / I/O — Input or bidirectional I/O pin 18 |
| Pin 4 | I17 / I/O — Input or bidirectional I/O pin 17 |
| Pin 5 | I16 / I/O — Input or bidirectional I/O pin 16 |
| Pin 6 | I15 / I/O — Input or bidirectional I/O pin 15 |
| Pin 7 | I14 / I/O — Input or bidirectional I/O pin 14 |
| Pin 8 | I13 / I/O — Input or bidirectional I/O pin 13 |
| Pin 9 | I12 / I/O — Input or bidirectional I/O pin 12 |
| Pin 10 | GND — Ground (0 V) |
| Pin 11 | I11 / I/O — Input or bidirectional I/O pin 11 |
| Pin 12 | I10 / I/O — Input or bidirectional I/O pin 10 |
| Pin 13 | I9 / I/O — Input or bidirectional I/O pin 9 |
| Pin 14 | I8 / I/O — Input or bidirectional I/O pin 8 |
| Pin 15 | I7 / I/O — Input or bidirectional I/O pin 7 |
| Pin 16 | I6 / I/O — Input or bidirectional I/O pin 6 |
| Pin 17 | I5 / I/O — Input or bidirectional I/O pin 5 |
| Pin 18 | I4 / I/O — Input or bidirectional I/O pin 4 |
| Pin 19 | I3 — Dedicated input 3 |
| Pin 20 | I2 — Dedicated input 2 |
| Pin 21 | I1 — Dedicated input 1 |
| Pin 22 | I0 — Dedicated input 0 |
| Pin 23 | NC — Not connected (per Classic EPLD datasheet) |
| Pin 24 | VCC — 5 V supply |
Typical Applications
EP610IPC-10 is suitable for 6 applications: Glue-Logic Consolidation (74LS Replacement), Address Decoding and Wait-State Generation, State-Machine Controllers, Bus-Interface Bridging (ISA/PCI/PMC to local bus), Legacy Telecom Backplane Glue Logic, Retro-Computing and Hobbyist Projects.
Glue-Logic Consolidation (74LS Replacement)
The EP610IPC-10's 300 usable gates and 16 macrocells can absorb the function of four to six discrete 74LS245/74LS373/74LS138 glue-logic ICs onto a single 24-pin PDIP. With 15 ns tPD and 100 MHz fMAX per the Altera datasheet, the part meets 8 MHz 8086/68k system-cycle budgets while reducing PCB area and inventory SKUs. Its 5 V CMOS I/O drives standard TTL loads directly, eliminating the need for level shifters when replacing legacy 74LS logic. Engineers typically target this use case when a printed-circuit-board redesign consolidates 4-6 SSI/MSI packages into one PLD to lower assembly cost and improve reliability.
Recommended
Address Decoding and Wait-State Generation
The EP610IPC-10 is widely deployed as an address decoder in 80C186, 68k, MIPS, and V60 embedded systems where it generates chip-selects and wait-state timing from a single 24-pin package. The 16 macrocells and 160 product terms support 4-6 fully decoded chip-select outputs with combinatorial or registered outputs, and the 15 ns tPD easily meets 25 MHz 80C186 hold-time requirements. According to the Classic EPLD datasheet, the AND-OR-NOT architecture is well suited to multi-input address decoding with sub-ns per-stage propagation. This remains a common retrofit requirement for industrial-control SBCs and legacy telecom backplanes.
Recommended
State-Machine Controllers
Each EP610IPC-10 macrocell contains a flip-flop plus feedback to the AND array, supporting Moore or Mealy state machines with 16 states and up to 16 outputs per device. The 5 V CMOS EPROM technology and 24-pin PDIP package make the part attractive for industrial control panels, traffic-light controllers, and appliance controllers where field-serviceability and through-hole construction are valued. Per the manufacturer datasheet, registered outputs can be clocked to 100 MHz, comfortably supporting serial-protocol bit-rate generators and stepper-motor sequencers. Engineers using ABEL or CUPL synthesis tools can port designs directly to MAX II CPLDs when modernizing.
Recommended
Bus-Interface Bridging (ISA/PCI/PMC to local bus)
The EP610IPC-10's 20 input pins and 16 I/O pins accommodate bidirectional bus bridges between legacy ISA/PCI bus signals and a local peripheral bus. Designers routinely pack a half-decode plus two bidirectional transceiver enables into a single Classic EPLD, using 5 V-tolerant I/O to interface directly to TTL-level control planes. Per the verified datasheet, the Turbo-only AND-OR-NOT architecture supports both combinatorial and registered outputs in the same device, simplifying mixed-bus interface logic. Typical targets are PMC carriers, VME single-board computers, and industrial PLC backplanes.
Recommended
Legacy Telecom Backplane Glue Logic
Long-lifecycle telecom systems (central-office switches, SONET/SDH add-drop multiplexers, and class-5 central-office line cards) deployed in the 1990s use the EP610IPC-10 for alarm-collection, line-card-control, and timing-distribution glue logic. The part's industrial -40C to +85C rating and 5 V operation match telecom environmental requirements, and the 24-pin PDIP through-hole construction is preferred for field-replaceable units. Per distributor listings, telecom carriers and CMs sourcing this part today typically work with surplus brokers to keep legacy systems in service until full lifecycle migration to MAX II/MAX V CPLDs.
Recommended
Retro-Computing and Hobbyist Projects
The EP610IPC-10 is a favorite among retro-computing enthusiasts building replica 8086, Z80, and 68k single-board computers where 5 V DIP-era logic matches the historical signal environment. Its 24-pin PDIP through-hole construction fits standard 0.1-inch breadboards and wire-wrap prototypes, and the part is still available from obsolete-component brokers at hobbyist-friendly prices. According to user reports on FPGAkey and classic-CPU forums, EP610IPC-10 designs can be programmed with modern ABEL/CUPL tools and Altera-compatible programmers, making it accessible for educational lab use and homebrew computer builds.
Recommended
Recommended Products Summary
Engineering reference data for EP610IPC-10 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610DC-10 | EP610DC-15 | EP610DI-10 | EP610DC-25 | EP610DM-35 | EP610DC-20 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 24-pin PDIP | 24-pin PDIP (ceramic DIP, OTP) - same footprint | 24-pin PDIP - same footprint | 24-pin PDIP (ceramic DIP, UV-erasable) - same footprint | 24-pin PDIP - same footprint | 24-pin PDIP (military grade) - same footprint | 24-pin PDIP - same footprint |
| Propagation Delay (tPD) | 15 ns | 10 ns (faster, pin-compatible) | 15 ns (identical) | 10 ns (faster, pin-compatible) | 25 ns (slower) | 35 ns (slowest) | 20 ns (slower) |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 300 | 300 | 300 | 300 | 300 | 300 | 300 |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | 0C to +70C (commercial) | -55C to +125C (military) | 0C to +70C (commercial) |
| Erase Method | UV-erasable (I grade) / OTP (C grade) | OTP (ceramic DIP) | OTP (ceramic DIP) | UV-erasable (ceramic DIP window) | OTP (ceramic DIP) | OTP (military) | OTP (ceramic DIP) |
| Lifecycle Status | Obsolete (discontinued) | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- UV-erasable industrial-temperature variant in 24-pin PDIP (vs EP610DC-10)
- Industrial temperature range within the EP610 family (vs EP610DC-15)
- Smallest Classic EPLD - replaces 4-6 PAL/GAL devices (vs EP910 (24-macrocell Classic))
Design Notes
The EP610IPC-10's -10 speed-grade suffix indicates the 15 ns commercial tPD bin; do not confuse with the -15 grade (which is the same 15 ns timing but in the -15 ordering code). When sourcing via second-hand brokers, verify the speed-grade marking on the package (e.g., 'IPC-10' vs 'IPC-15') to ensure timing compliance. Using an -25 or -35 grade in a -10 socket will silently slow the design and may break hold-time margins.
The EP610IPC-10 requires a stable 5 V supply with a 0.1 uF decoupling capacitor placed within 5 mm of the VCC pin (pin 24) and a bulk 10 uF tantalum capacitor on the same 5 V rail. Per the Classic EPLD datasheet, VCC rise time should be monotonic for proper initialization of the EPROM configuration latches. Power-rail sequencing is not required, but VCC droop below 4.5 V during programming can corrupt the JEDEC fuse map.
Keep high-frequency signal traces on adjacent layers at least 0.2 mm away from EP610IPC-10 I/O pins to minimize crosstalk. Place unused I/O pins in a defined logic state (input with pull-up or output driving a known level) per the Classic EPLD datasheet; floating inputs can draw excess supply current and inject noise into the AND array. Pin 23 (NC) may be grounded or left floating on the PCB without affecting operation.
Designs ported from older 20-pin PAL/GAL devices often assume registered outputs with positive-edge clocks; the EP610IPC-10 macrocell supports both D and T flip-flops plus configurable clock polarity, but pin assignments must be respected during ABEL/CUPL compilation. Verify the JEDEC fuse map output by your synthesis tool against the Classic EPLD datasheet pinout before programming, as silent mis-mapping (e.g., output on a dedicated input pin) is a common source of first-power-on failures.
Compliance Information
EP610IPC-10 is an obsolete Altera Classic EPLD with no verified RoHS/REACH documentation in the available web data; original Altera datasheet pre-dates RoHS enforcement. For new designs in RoHS-restricted regions, source a MAX II/MAX V CPLD with verified compliance.
