EP610IPC-25 vs EP610IPC-10 Comparison
Detailed side-by-side comparison of EP610IPC-25 by Intel and EP610IPC-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IPC-25 | EP610IPC-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.85 | $16.40 |
| Family | Classic EPLD (EP610) | Altera Classic EPLD |
| Architecture | PAL-type, CMOS, Erasable | Turbo-only AND-OR-NOT, PAL-type |
| Propagation Delay (tpd) | 25 ns (max) | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Maximum Inputs | 20 | β |
| Maximum I/O Pins | 16 | β |
| Dedicated Outputs | 16 | β |
| Product Terms | 160 | 160 total |
| Operating Temperature | 0 Β°C to +70 Β°C (Commercial) | -40C to +85C (industrial) |
| Package | 24-pin PDIP (Plastic DIP) | 24-pin PDIP (Plastic DIP) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | CMOS EPROM (UV-erasable / OTP) |
| TTL Compatibility | 100% TTL emulation | β |
| Mounting Type | Through-Hole | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | Non-compliant (contains Pb, PDIP package) | β |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | β |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| Programmable Gates | β | 300 usable gates |
| Macrocells | β | 16 |
| Maximum Operating Frequency | β | 100 MHz |
| Propagation Delay (tPD) | β | 15 ns (commerical -10 grade) |
| Dedicated Inputs | β | 4 |
| I/O Pins | β | 16 |
| Total Input Pins | β | 20 |
| Supply Voltage | β | 5 V |
| Programming Method | β | Altera programming hardware (UV erase for I grade, OTP for C grade) |
| TTL Emulation | β | 100% TTL compatible |