EP610JI-30 vs EP610LC-30 Comparison
Detailed side-by-side comparison of EP610JI-30 by Altera and EP610LC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610JI-30 | EP610LC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.40 | $16.40 |
| Family | Altera Classic EPLD (EP610) | Classic EPLD (EP610) |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | β |
| Macrocells | 16 | β |
| Propagation Delay (tpd) | 30 ns (max) | β |
| Pipelined Data Rate | Up to 100 MHz | up to 100 MHz |
| Product Terms | 160 | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 16 | β |
| External Clocks | 2 | β |
| Supply Voltage | 5 V (single supply) | β |
| Process Technology | CMOS | β |
| Package | CQCC28 (windowed ceramic JLCC, J-bend) | 24-pin CERDIP / PDIP |
| Package Code | JLCC-28 / CQCC28 | β |
| Erasure Method | Ultraviolet (UV) via top window | β |
| Programming | Altera Logic Programmer compatible | β |
| Operating Temperature | -40C to +85C (industrial, per EP610 family suffix convention) | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Mounting Type | Surface Mount (JLCC) | Through-Hole |
| RoHS Status | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Macro Cells | β | 16 |
| Logic Gates | β | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | β | 30 ns |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | β | 13 V nominal |
| Technology | β | CMOS EPROM (UV-erasable) |
| Erase/Program Cycles | β | 1000 typical |
| Output Type | β | CMOS tri-state (programmable) |
| Logic Compatibility | β | TTL and CMOS |
| Turbo Mode | β | Yes (registered path bypass) |