EP610JI-30 - 16-Macrocell Classic EPLD, 30ns, CQCC28 Windowed | Altera
MPN: EP610JI-30 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $15.2 | $152.00 |
| 100 | $12.8 | $1,280.00 |
| 500 | $10.95 | $5,475.00 |
| 1,000 | $9.4 | $9,400.00 |
EP610JI-30 Overview
A Classic EPLD (Erasable Programmable Logic Device) is a UV-erasable member of the programmable logic family, sitting between simple PAL/GAL devices and modern CPLDs/FPGAs in the design complexity hierarchy (PAL/GAL -> Classic EPLD -> MAX CPLD -> FPGA). The windowed ceramic package contains a quartz window that allows the device's internal EPROM configuration memory to be erased with ultraviolet light, enabling hundreds of reprogramming cycles during prototyping and design iteration. The 16-macrocell Classic architecture is sum-of-products based, with a global bus interconnecting the AND/OR arrays to a programmable output macrocell register bank.
Key features of the EP610JI-30 include the 32 ns propagation delay window (often marketed as 30 ns grade per the speed suffix), 100 MHz pipeline throughput, JTAG-free boundary-scan-free classic programming via the Altera programming algorithm, and 5 V CMOS I/O. The device supports bidirectional I/O, programmable output enables, and registers on every macrocell, making it a flexible glue-logic replacement for discrete TTL/CMOS gate arrays in legacy designs. Two clock inputs feed the device's internal register clock network.
The EP610 architecture uses an EPROM-based sum-of-products structure with a programmable interconnect array feeding 16 output macrocells. Each macrocell contains a programmable flip-flop, output polarity selection, and tri-state control. This architecture gives deterministic tpd that does not depend on routing congestion, a major advantage over early FPGA architectures of the same era, and the part supports synchronous and asynchronous clocking schemes with predictable pin-to-pin timing.
Typical applications for the EP610JI-30 include legacy bus-interface glue logic, address decoding for M68000/i8086 systems, state-machine replacement in industrial controllers, TTL/CMOS gate-array consolidation, and prototyping of glue logic where modern FPGAs are not required. The windowed package is specifically chosen for engineering development and low-volume production where in-house UV erasure and reprogramming provide the lowest total cost.
When designing with this part, note that the EP610 requires an Altera-compatible programmer (e.g., Altera Logic Programmer or third-party equivalents). Decoupling must use a 0.1 microfarad ceramic capacitor per VCC pin placed within 5 mm of the package. Inputs float when not driven; tie unused inputs to VCC or GND through a 10 kohm resistor to avoid CMOS shoot-through current.
This page synthesizes distributor stock status, JLCC28 package diagrams, and pin-compatible Classic EPLD alternatives not consolidated in the original Altera datasheet, helping sourcing engineers extend the lifecycle of legacy Classic EPLD designs.
Drop-in alternatives for EP610JI-30 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610JI-30 (same form factor and footprint) β differing in Package, Family, Mounting Type, Process Technology, Supply Voltage (VCC).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP610JI-25
β Drop-Inπ Reference alternative (not in catalog)
EP610LI-30
β Drop-Inβ In Stock
$18.5 / Unit
View Datasheet βEP610LI-12
β Drop-Inπ Reference alternative (not in catalog)
EP610ILC-10
β Drop-Inβ In Stock
$7.2 / Unit
View Datasheet βEP610ILC-25
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEP610IPC-10
β Drop-Inβ In Stock
$16.4 / Unit
View Datasheet βEP610JI-30 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD (EP610) |
| Device Type | UV Erasable Programmable Logic Device (EPLD) |
| Macrocells | 16 |
| Propagation Delay (tpd) | 30 ns (max) |
| Pipelined Data Rate | Up to 100 MHz |
| Product Terms | 160 |
| Dedicated Inputs | 4 |
| I/O Pins | 16 |
| External Clocks | 2 |
| Supply Voltage | 5 V (single supply) |
| Process Technology | CMOS |
| Package | CQCC28 (windowed ceramic JLCC, J-bend) |
| Package Code | JLCC-28 / CQCC28 |
| Erasure Method | Ultraviolet (UV) via top window |
| Programming | Altera Logic Programmer compatible |
| Operating Temperature | -40C to +85C (industrial, per EP610 family suffix convention) |
| Mounting Type | Surface Mount (JLCC) |
EP610JI-30 Pin Configuration
| Pin 1 | INPUT/CLK1 β Dedicated input / Clock 1 |
| Pin 2 | INPUT/CLK2 β Dedicated input / Clock 2 |
| Pin 3 | INPUT β Dedicated input |
| Pin 4 | INPUT β Dedicated input |
| Pin 5 | I/O β Bidirectional I/O macrocell |
| Pin 6 | I/O β Bidirectional I/O macrocell |
| Pin 7 | I/O β Bidirectional I/O macrocell |
| Pin 8 | I/O β Bidirectional I/O macrocell |
| Pin 9 | I/O β Bidirectional I/O macrocell |
| Pin 10 | I/O β Bidirectional I/O macrocell |
| Pin 11 | I/O β Bidirectional I/O macrocell |
| Pin 12 | I/O β Bidirectional I/O macrocell |
| Pin 13 | VCC β 5 V supply |
| Pin 14 | I/O β Bidirectional I/O macrocell |
| Pin 15 | I/O β Bidirectional I/O macrocell |
| Pin 16 | I/O β Bidirectional I/O macrocell |
| Pin 17 | I/O β Bidirectional I/O macrocell |
| Pin 18 | I/O β Bidirectional I/O macrocell |
| Pin 19 | I/O β Bidirectional I/O macrocell |
| Pin 20 | I/O β Bidirectional I/O macrocell |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β Bidirectional I/O macrocell |
| Pin 23 | I/O β Bidirectional I/O macrocell |
| Pin 24 | I/O β Bidirectional I/O macrocell |
| Pin 25 | I/O β Bidirectional I/O macrocell |
| Pin 26 | I/O β Bidirectional I/O macrocell |
| Pin 27 | I/O β Bidirectional I/O macrocell |
| Pin 28 | I/O β Bidirectional I/O macrocell |
Typical Applications
EP610JI-30 is suitable for 6 applications: Legacy M68000/i8086 Bus Address Decoding, Industrial State-Machine Replacement, TTL/CMOS Gate Array Consolidation, VMEbus and Multibus Interface Logic, Aerospace Flight-Control Prototyping, Test & Measurement Instrument Front-End Logic.
Legacy M68000/i8086 Bus Address Decoding
The EP610JI-30's 16 macrocells and 160 product terms make it an ideal fit for legacy 16-bit and 32-bit microprocessor bus address decoding. With 30 ns tpd it cleanly decodes addresses at 25 MHz system clocks typical of M68000 and i8086 designs. The windowed ceramic package supports UV erasure for prototyping multiple address map variations during development. Place the part between the address bus and chip-select lines of peripheral devices to replace discrete 74LS/74F glue logic. The 5 V CMOS I/O levels are fully TTL-compatible, eliminating the need for level translation buffers in legacy systems. Two external clock inputs allow synchronous chip-select generation synchronized to the system clock.
Recommended
Industrial State-Machine Replacement
Replace discrete TTL/CMOS state machines with the EP610JI-30 to consolidate 4-8 packages into a single Classic EPLD. With 16 macrocells and 160 product terms, the part handles typical 8-state Mealy or Moore machines plus output combinational logic. The 30 ns tpd is fast enough for industrial PLC scan times of 10 ms or shorter. Industrial temperature grade (per the 'I' suffix) and ceramic packaging support operation in harsh factory environments. Use the JTAG-free Altera Logic Programmer to develop and burn the state machine during prototyping, with the windowed package enabling UV erasure for design iteration. Five-volt CMOS operation matches legacy industrial control voltages without translation.
Recommended
TTL/CMOS Gate Array Consolidation
Consolidate 20-30 discrete 74LS00/74F00-series gates into one EP610JI-30 Classic EPLD, saving PCB area and reducing power consumption. Each macrocell implements a registered sum-of-products function with tri-state control, replacing combinational gates, latches, and flip-flops. The 30 ns tpd matches or exceeds standard 74LS speeds for most glue-logic functions. The windowed CQCC28 package supports in-house UV erasure, allowing multiple design revisions during development without chip replacement cost. Five-volt CMOS I/O with TTL-compatibility eliminates the need for mixed-voltage buffers in legacy systems.
Recommended
VMEbus and Multibus Interface Logic
Implement VMEbus or Multibus interface arbitration, bus grant daisy-chaining, and interrupt acknowledgement logic with the EP610JI-30. The 16 I/O lines and 4 dedicated inputs provide enough capacity for bus request/grant logic plus interrupt vector generation. Thirty nanosecond propagation delay handles VMEbus DTB cycles at full speed, and the 5 V supply matches VMEbus 5 V rails. The windowed ceramic CQCC28 package was the original Altera-recommended solution for VMEbus interface prototyping in the late 1980s and early 1990s. Two external clock inputs can be wired to VMEbus BCLK and a system clock for synchronous arbitration.
Recommended
Aerospace Flight-Control Prototyping
Prototype flight-control and avionics logic with the EP610JI-30, leveraging its industrial temperature grade and ceramic packaging for harsh-environment tolerance. The 16-macrocell capacity handles typical actuator control loops and sensor signal routing in pre-production designs. Thirty nanosecond propagation delay supports flight-control loop rates of 1 kHz or higher. The windowed CQCC28 package supports hundreds of UV erase/reprogram cycles during safety-critical verification. Five-volt CMOS operation matches avionics power bus standards without additional regulation.
Recommended
Test & Measurement Instrument Front-End Logic
Implement range selection, signal routing, and timing control in bench-top test and measurement instruments using the EP610JI-30. Sixteen macrocells handle multiplexed input switching, A/D range control, and trigger logic. Thirty nanosecond tpd supports real-time trigger generation for oscilloscope-grade instruments. The windowed CQCC28 package supports design iteration during prototype development without chip cost. Five-volt CMOS I/O interfaces directly with legacy ADC/DAC front-ends. Two external clocks accept sample-clock and reference-clock inputs for synchronous acquisition systems.
Recommended
Recommended Products Summary
Engineering reference data for EP610JI-30 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610JI-25 | EP610LI-30 | EP610LI-12 | EP610ILC-10 | EP610ILC-25 | EP610IPC-10 |
|---|---|---|---|---|---|---|---|
| Package | CQCC28 (JLCC-28, windowed ceramic) | CQCC28 (JLCC-28, windowed ceramic) | CQCC28 (JLCC-28) | CQCC28 (JLCC-28) | CQCC28 (JLCC-28) | CQCC28 (JLCC-28) | CQCC28 (JLCC-28) |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tpd) | 30 ns | 25 ns (-17%) | 30 ns (same) | 12 ns (-60%) | 10 ns (-67%) | 25 ns (-17%) | 10 ns (-67%) |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
| Product Terms | 160 | 160 | 160 | 160 | 160 | 160 | 160 |
| Dedicated Inputs | 4 | 4 | 4 | 4 | 4 | 4 | 4 |
| I/O Pins | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
| External Clocks | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Windowed ceramic package supports UV erasure for design iteration (vs Plastic one-time-programmable (OTP) PAL/GAL parts)
- Deterministic 30 ns tpd independent of routing congestion (vs Early FPGA architectures of the same era)
- 16 macrocells and 160 product terms in a single 28-pin package (vs Discrete 74LS00/74F00-series TTL gates)
Design Notes
Decoupling: Place a 0.1 microfarad ceramic bypass capacitor within 5 mm of every VCC pin (pin 13 in CQCC28). Add a bulk 10 microfarad tantalum or aluminum electrolytic capacitor at the board's power entry point to support the EP610JI-30's CMOS switching transients. Ground pin 21 must connect to a low-impedance ground plane; avoid daisy-chained ground traces that create switching noise.
Unused CMOS inputs must not float - tie them to VCC or GND through a 10 kohm resistor to prevent shoot-through current that can exceed 1 mA per pin and shift tpd. Outputs left in tri-state should have a 10 kohm pull-up. Programming pins (where present on the package variant) must be driven to defined logic levels during normal operation; refer to the EP610 family datasheet for the exact pin assignments in the CQCC28 package.
Estimated: At 30 ns tpd, the EP610JI-30 has a 33 MHz maximum toggle frequency, suitable for legacy 8/16-bit bus designs. For traces longer than 50 mm, add 22 ohm series damping resistors at outputs to control ringing on the 5 V CMOS signal edges (estimated edge rate 2-3 ns). Keep I/O traces short and avoid running them parallel to clock traces to minimize crosstalk into the 5 V CMOS receivers.
Compliance Information
The EP610JI-30 ships in a vintage windowed ceramic CQCC28 package. RoHS, REACH, lead-free, and halogen-free status are not stated in current distributor data; ceramic/leaded construction typical of early 1990s EPLDs suggests non-RoHS. AEC-Q100 not applicable for this legacy programmable logic device class.
