EP610JI-30 vs EP610LI-35 Comparison
Detailed side-by-side comparison of EP610JI-30 by Altera and EP610LI-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610JI-30 | EP610LI-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.40 | $10.50 |
| Family | Altera Classic EPLD (EP610) | Classic EPLD |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | β |
| Macrocells | 16 | β |
| Propagation Delay (tpd) | 30 ns (max) | β |
| Pipelined Data Rate | Up to 100 MHz | Up to 100 MHz |
| Product Terms | 160 | 160 |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 | β |
| External Clocks | 2 | β |
| Supply Voltage | 5 V (single supply) | 5 V |
| Process Technology | CMOS | CMOS |
| Package | CQCC28 (windowed ceramic JLCC, J-bend) | 28-pin PLCC (windowed ceramic, 'LI') |
| Package Code | JLCC-28 / CQCC28 | β |
| Erasure Method | Ultraviolet (UV) via top window | β |
| Programming | Altera Logic Programmer compatible | β |
| Operating Temperature | -40C to +85C (industrial, per EP610 family suffix convention) | β |
| Mounting Type | Surface Mount (JLCC) | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Series | β | EP610 |
| Number of Macrocells | β | 16 |
| Usable Gates | β | 300 |
| Number of I/O Pins | β | 16 |
| Total Inputs | β | 20 |
| External Clock Inputs | β | 2 |
| Maximum Propagation Delay | β | 35 ns (tpd) |
| Maximum Operating Frequency | β | 28.6 MHz (fmax) |
| Architecture | β | PAL-type (AND-OR array) |
| Operating Temperature Range | β | [DATA_NEEDED: military/industrial operating temperature range] |
| Programming Technology | β | UV-erasable (EPROM) |