EP610LC-30 vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610LC-30 by Intel and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-30 | EP610DC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $18.40 |
| Family | Classic EPLD (EP610) | Altera Classic EP610 |
| Macro Cells | 16 | β |
| Logic Gates | Equivalent to 300 gates (typical) | β |
| Pin-to-Pin Delay (tPD) | 30 ns | β |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Programming Voltage (VPP) | 13 V nominal | β |
| Technology | CMOS EPROM (UV-erasable) | β |
| Package | 24-pin CERDIP / PDIP | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Operating Temperature | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Erase/Program Cycles | 1000 typical | β |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Output Type | CMOS tri-state (programmable) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Logic Compatibility | TTL and CMOS | β |
| Turbo Mode | Yes (registered path bypass) | β |
| Device Type | β | CPLD - Classic EPLD |
| Macrocells | β | 16 |
| Usable Gates | β | 300 |
| Propagation Delay (tPD) | β | 35 ns |
| Maximum Frequency (fMAX) | β | 28.6 MHz |
| Process Technology | β | CMOS |
| Program/erase Method | β | UV-erasable (windowed CERDIP) |
| Manufacturer | β | Originally Altera; today supplied via Rochester Electronics (authorized) |