EP610LC-30 vs EP610JI-30 Comparison
Detailed side-by-side comparison of EP610LC-30 by Intel and EP610JI-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-30 | EP610JI-30 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $9.40 |
| Family | Classic EPLD (EP610) | Altera Classic EPLD (EP610) |
| Macro Cells | 16 | β |
| Logic Gates | Equivalent to 300 gates (typical) | β |
| Pin-to-Pin Delay (tPD) | 30 ns | β |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Programming Voltage (VPP) | 13 V nominal | β |
| Technology | CMOS EPROM (UV-erasable) | β |
| Package | 24-pin CERDIP / PDIP | CQCC28 (windowed ceramic JLCC, J-bend) |
| Operating Temperature | 0 C to +70 C (commercial) / -55 C to +125 C (military) | -40C to +85C (industrial, per EP610 family suffix convention) |
| Erase/Program Cycles | 1000 typical | β |
| Mounting Type | Through-Hole | Surface Mount (JLCC) |
| Output Type | CMOS tri-state (programmable) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Logic Compatibility | TTL and CMOS | β |
| Turbo Mode | Yes (registered path bypass) | β |
| Device Type | β | UV Erasable Programmable Logic Device (EPLD) |
| Macrocells | β | 16 |
| Propagation Delay (tpd) | β | 30 ns (max) |
| Product Terms | β | 160 |
| Dedicated Inputs | β | 4 |
| I/O Pins | β | 16 |
| External Clocks | β | 2 |
| Supply Voltage | β | 5 V (single supply) |
| Process Technology | β | CMOS |
| Package Code | β | JLCC-28 / CQCC28 |
| Erasure Method | β | Ultraviolet (UV) via top window |
| Programming | β | Altera Logic Programmer compatible |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |