EP610LC-30 vs EP610LC15 Comparison
Detailed side-by-side comparison of EP610LC-30 by Intel and EP610LC15 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester
EP610LC15 ObsoleteSpecification Comparison
| Parameter | EP610LC-30 | EP610LC15 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $5.45 |
| Family | Classic EPLD (EP610) | β |
| Macro Cells | 16 | β |
| Logic Gates | Equivalent to 300 gates (typical) | β |
| Pin-to-Pin Delay (tPD) | 30 ns | β |
| Pipelined Data Rate | up to 100 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (Β±10%) |
| Programming Voltage (VPP) | 13 V nominal | β |
| Technology | CMOS EPROM (UV-erasable) | UV-erasable EPROM, CMOS |
| Package | 24-pin CERDIP / PDIP | PLCC-28 (J-Lead) |
| Operating Temperature | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0 Β°C to +70 Β°C (LC suffix = commercial) |
| Erase/Program Cycles | 1000 typical | β |
| Mounting Type | Through-Hole | β |
| Output Type | CMOS tri-state (programmable) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (Rochester re-creation) |
| Logic Compatibility | TTL and CMOS | β |
| Turbo Mode | Yes (registered path bypass) | β |
| Device Family | β | Classic EPLD (EP610) |
| Number of Macrocells | β | 16 |
| Number of Usable Gates | β | [DATA_NEEDED: usable gate count] |
| Propagation Delay (tPD) | β | 15 ns |
| Maximum Toggle Frequency (fMAX) | β | 83.3 MHz |
| Dedicated Inputs | β | 10 |
| I/O Pins | β | 16 |
| Total Logic Pins | β | 24 |
| Programming Interface | β | Altera 4-pin serial (Classic algorithm) |
| Security Bit | β | Yes (programmable) |