EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester
MPN: EP610LC15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.5 | $8.50 |
| 10 | $7.65 | $76.50 |
| 100 | $6.8 | $680.00 |
| 500 | $6.1 | $3,050.00 |
| 1,000 | $5.45 | $5,450.00 |
EP610LC15 Overview
A CPLD/EPLD is a non-volatile programmable logic device that combines multiple PAL-style macrocell arrays on a single die, allowing designers to replace dozens of 74-series SSI/MSI glue-logic packages with a single erasable part. EPLDs sit in the broader taxonomy programmable logic device (PLD) -> EPLD/CPLD -> CMOS programmable logic -> digital semiconductor, and historically predate modern flash-based CPLDs and SRAM-based FPGAs. The Classic architecture uses a sum-of-products AND-OR array followed by an output macrocell with selectable flip-flop polarity, making it well suited for state machines, address decoding, and bus interface logic.
Key features of the EP610LC15 include 16 macrocells, 10 dedicated inputs, 16 I/O pins forming a 24-pin logic array, a 15 ns pin-to-pin propagation delay (tPD), a 83.3 MHz maximum toggle frequency, and a single 5V (±10%) supply with TTL-compatible I/O. The device is in-system programmable via the Altera-standard 4-pin JTAG-style serial interface and supports security-bit protection to lock the programmed pattern.
The EP610 architecture uses an EPROM-based AND array driving a fixed OR array, with each macrocell containing a programmable flip-flop, output enable, and feedback path. The 5V CMOS process yields zero standby current on disabled outputs and typical quiescent current in the low milliamp range, while the ceramic-windowed package allows pattern erasure under UV light for prototyping and design iteration.
Typical applications include bus decoding for 8086/68000 microprocessor systems, address decoding for memory and peripheral mapping, state-machine implementation in industrial controllers, and TTL-to-CMOS level-interface bridging in legacy 5V designs. The 83.3 MHz fMAX also supports small pipelined datapath functions such as counter chains, frequency dividers, and shift registers.
When designing with the EP610LC15, observe that the LC suffix denotes the commercial 0°C to +70°C operating range and the 15 ns speed grade; the -15 speed bin is the slowest of the EP610 family and should be selected only when timing slack allows. Programming requires a hardware programmer supporting the Classic EPLD algorithm (e.g., Altera PL-ASAP or Data I/O). Lead-finish options are matte-tin over nickel (lead-free) per modern Rochester Electronics re-creation, RoHS compliant.
This page consolidates Rochester Electronics and Altera datasheet specs, cross-brand 5V-CPLD drop-in candidates, and design notes for legacy 5V glue-logic replacement that distributor listings do not present in one place.
Drop-in alternatives for EP610LC15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610LC15 (same form factor and footprint) — differing in Package, Technology, Operating Temperature, Mounting Type, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610LC-35
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610LC-30
✅ Drop-In✓ In Stock
$16.4 / Unit
View Datasheet →EP610LC-25
✅ Drop-In✓ In Stock
$6.2 / Unit
View Datasheet →EP610DC-15
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EP610ILC-10
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EP610IPC-25
✅ Drop-In✓ In Stock
$8.85 / Unit
View Datasheet →EP610LC15 Maximum Ratings & Electrical Characteristics
| Device Family | Classic EPLD (EP610) |
| Number of Macrocells | 16 |
| Propagation Delay (tPD) | 15 ns |
| Maximum Toggle Frequency (fMAX) | 83.3 MHz |
| Supply Voltage (VCC) | 5 V (±10%) |
| Dedicated Inputs | 10 |
| I/O Pins | 16 |
| Total Logic Pins | 24 |
| Technology | UV-erasable EPROM, CMOS |
| Package | PLCC-28 (J-Lead) |
| Operating Temperature | 0 °C to +70 °C (LC suffix = commercial) |
| Programming Interface | Altera 4-pin serial (Classic algorithm) |
| Security Bit | Yes (programmable) |
| RoHS Status | Compliant (Rochester re-creation) |
EP610LC15 Pin Configuration
| Pin 1 | I/O0 — Bidirectional I/O macrocell 0 |
| Pin 2 | I/O1 — Bidirectional I/O macrocell 1 |
| Pin 3 | I/O2 — Bidirectional I/O macrocell 2 |
| Pin 4 | I/O3 — Bidirectional I/O macrocell 3 |
| Pin 5 | I/O4 — Bidirectional I/O macrocell 4 |
| Pin 6 | I/O5 — Bidirectional I/O macrocell 5 |
| Pin 7 | I/O6 — Bidirectional I/O macrocell 6 |
| Pin 8 | I/O7 — Bidirectional I/O macrocell 7 |
| Pin 9 | IN8 — Dedicated input 8 |
| Pin 10 | GND — Ground |
| Pin 11 | IN9 — Dedicated input 9 |
| Pin 12 | MODE — Programming mode select |
| Pin 13 | SCLK — Serial programming clock |
| Pin 14 | SDI — Serial data input (programming) |
| Pin 15 | SDO — Serial data output (programming/verify) |
| Pin 16 | I/O15 — Bidirectional I/O macrocell 15 |
| Pin 17 | I/O14 — Bidirectional I/O macrocell 14 |
| Pin 18 | I/O13 — Bidirectional I/O macrocell 13 |
| Pin 19 | I/O12 — Bidirectional I/O macrocell 12 |
| Pin 20 | I/O11 — Bidirectional I/O macrocell 11 |
| Pin 21 | I/O10 — Bidirectional I/O macrocell 10 |
| Pin 22 | I/O9 — Bidirectional I/O macrocell 9 |
| Pin 23 | I/O8 — Bidirectional I/O macrocell 8 |
| Pin 24 | IN7 — Dedicated input 7 |
| Pin 25 | IN6 — Dedicated input 6 |
| Pin 26 | IN5 — Dedicated input 5 |
| Pin 27 | IN4 — Dedicated input 4 |
| Pin 28 | VCC — +5 V supply |
Typical Applications
EP610LC15 is suitable for 6 applications: Microprocessor Address Decoding, Glue-Logic Integration in 5V Industrial Controllers, Legacy TTL-to-CMOS Level Interface Bridge, Pipelined Datapath and Frequency Divider, Vintage Computing Expansion Card Logic, Legacy Telecom Line-Card State Machine.
Microprocessor Address Decoding
The EP610LC15 fits 8086/68000/80386 address-decoding roles because its 24 logic pins and 16 macrocells can express full-chip-select, memory-bank and wait-state logic in a single device. Designers feed the upper address bus into the 10 dedicated inputs and route decoded chip-enables through the 16 I/O macrocells, replacing 4-6 standard 74LS138/139/32 packages. The 15 ns tPD plus 5 ns output delay budget fits one address-decode stage inside a 33 MHz 80386 cycle (30 ns), and the EPROM non-volatility means decode maps survive power cycles without external configuration memory. Compared to discrete SSI/MSI, the EP610LC15 also lets engineers revise the decode map by re-erasing (UV on windowed parts) instead of re-wiring.
Recommended
Glue-Logic Integration in 5V Industrial Controllers
In 5V PLC and process-control boards, the EP610LC15 replaces scattered 74LS/74HC glue by integrating latches, multiplexers, parity generators and small state machines into one 5V part. Its 5 V TTL-compatible I/O directly interfaces with legacy 8255 PPI, 8251 USART and 8253/54 timer peripherals without level translation, and the 16 macrocells comfortably hold a typical 8-12 state FSM plus surrounding decoding. The 83.3 MHz fMAX lets the EPLD handle time-multiplexed bus steering at ISA-bus-like speeds, while the LC commercial 0-70°C range suits cabinet-mounted controllers. Field-upgradeable UV-windowed units allow field re-programming during commissioning.
Recommended
Legacy TTL-to-CMOS Level Interface Bridge
The EP610LC15 serves as a bidirectional level-shift and protocol-conversion bridge between 5V TTL and 5V CMOS logic islands, because its macrocell output enables can be configured as open-drain with external pull-up for slow-speed interfaces. With 16 I/O pins the EPLD can translate a full 8-bit data bus plus 4 handshaking lines, while the 15 ns tPD adds minimal latency to memory-mapped peripheral cycles. Designers commonly pair it with a 74HCT245 buffer for higher drive strength, and the EPROM non-volatility ensures the bridge comes up configured on every power cycle. This is also a common technique for retrocomputing adapter boards and FPGA test fixtures.
Recommended
Pipelined Datapath and Frequency Divider
The 83.3 MHz fMAX and 16 flip-flop-equipped macrocells allow the EP610LC15 to implement small synchronous pipelines, binary counters, and frequency dividers in instrumentation and telecom line cards. A typical 8-bit synchronous counter with registered carry consumes roughly 8 macrocells and toggles cleanly at the fMAX limit, well above the 15 ns tPD-combinational-logic path it can wrap around. Because outputs are registered by default, the EPLD produces low-skew clocks without external PLL hardware, which is valuable in legacy 5V designs where modern clock-generator ICs are unavailable. The LC commercial temperature grade suits indoor bench equipment and central-office telecom.
Recommended
Vintage Computing Expansion Card Logic
Retrocomputing projects (ISA bus cards, Amiga/Z80 bus adapters, Apple II peripheral emulators) frequently use the EP610LC15 to implement custom I/O decoding and bus-master glue in 5V environments. Its 28-pin PLCC package is breadboard-friendly via low-cost PLCC sockets, and the windowed ceramic variant allows hobbyists to erase and re-program patterns under UV light during iterative development. The 16 macrocells and 24 logic pins are enough to decode 16-bit I/O port ranges plus IRQ/DMA handshake, and the 5V TTL I/O is fully compatible with vintage bus levels. Compared to re-implementing in a modern FPGA, the EP610LC15 keeps the design period-authentic and avoids needing 3.3V-to-5V adapters.
Recommended
Legacy Telecom Line-Card State Machine
Central-office telecom line cards built in the 1990s rely on 5V EPLDs like the EP610LC15 for hook-state detection glue, ringing-relay sequencing, and codec interface control. The 16 macrocells hold a 10-12 state FSM with sufficient headroom for revision bits, and the 15 ns tPD easily meets the 8 kHz PCM frame budget with margin to spare. Because the part is non-volatile (EPROM-based), line cards come up in a known state after power-cycle or brown-out, which is critical for SLIC survivability. Rochester Electronics' continuing-manufacture status ensures these mature line cards remain serviceable well past their original end-of-life.
Recommended
Recommended Products Summary
Engineering reference data for EP610LC15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610LC-35 | EP610LC-25 | EP610DC-15 | EP610ILC-10 |
|---|---|---|---|---|---|
| Brand | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics |
| Package | PLCC-28 | PLCC-28 - same | PLCC-28 - same | PLCC-28 - same | PLCC-28 - same |
| Macrocells | 16 | 16 | 16 | 16 | 16 |
| Propagation Delay (tPD) | 15 ns | 35 ns (+133%) | 25 ns (+67%) | 15 ns (identical) | 10 ns (-33%) |
| Max Toggle Frequency | 83.3 MHz | 28.5 MHz | 50 MHz | 83.3 MHz | 100 MHz |
| Supply Voltage | 5 V (±10%) | 5 V (±10%) | 5 V (±10%) | 5 V (±10%) | 5 V (±10%) |
| Operating Temperature | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (commercial, ceramic) | -40 °C to +85 °C (industrial) |
| Pin-to-Pin Compatible | Reference | Yes (drop-in) | Yes (drop-in) | Yes (drop-in) | Yes (drop-in) |
Key Differentiators
- 15 ns tPD - fastest grade in the 5V Classic EP610 EPLD family (vs EP610LC-25)
- Industry-standard Classic EPLD with Rochester Electronics continuing-manufacture support (vs EP610LC-35 (Rochester))
- PLCC-28 plastic J-lead package vs ceramic-windowed variant (vs EP610DC-15 (ceramic-windowed))
Design Notes
Estimated: at 83.3 MHz with all 16 outputs toggling at full CMOS load (50 pF each), the EP610LC15 draws roughly 80-120 mA from VCC, plus a DC quiescent of 5-10 mA on disabled outputs. Use a 0.1 µF ceramic decoupling capacitor within 5 mm of the VCC pin (pin 28) plus a 10 µF bulk tantalum on the same 5 V rail. Keep the GND pin (pin 10) return path short and direct to the ground plane; the Classic EPLD's high-speed output edges (~2 ns) will create ground bounce if the return inductance exceeds 5 nH.
Do not confuse the EP610LC15 (commercial PLCC-28, 15 ns) with the EP610PC15 (commercial PDIP-24 in some second-source listings) - the packages differ and they are NOT pin-compatible drop-ins. Also note that the 'LC' suffix indicates 0-70°C commercial; for industrial -40-85°C operation you must order the EP610ILC10, EP610ILC-25 or EP610ILI-12. Programming requires a Classic EPLD programmer (Altera PL-ASAP, Data I/O Model 29B or BP Micro programmer with Classic algorithm); modern JTAG-only programmers do NOT support this part.
Route the four serial programming pins (SDI, SDO, SCLK, MODE) as a group away from high-frequency switching signals to prevent programming noise coupling. The EP610LC15 has no internal pull-ups on programming pins, so external 10 kΩ pull-ups on MODE and SCLK prevent floating-state programming-mode lockup. For socketed designs (PLCC-28 sockets are common), specify a low-profile machined-pin socket to maintain signal integrity at 83.3 MHz fMAX; standard stamped sockets add ~1 nH per contact which can erode timing margin.
Compliance Information
Rochester Electronics re-creation is RoHS compliant with matte-tin lead finish over nickel; original Altera Classic EPLDs were non-RoHS. Not AEC-Q100 qualified - automotive applications should use modern CPLD/FPGA families. Continued manufacture under Rochester Electronics' last-time-buy and continuing-manufacture programs as of 2026-09-10.
