EP610LC-35 vs EP610LC-30 Comparison

Detailed side-by-side comparison of EP610LC-35 by Altera and EP610LC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610LC-35 EP610LC-30
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $16.40
Family Altera Classic EPLD Classic EPLD (EP610)
Device Series EP610 β€”
Macrocells 16 β€”
Usable Gates 300 β€”
Propagation Delay (tpd) 37 ns β€”
Supply Voltage (Vcc) 5 V β€”
Technology CMOS EEPROM (one-time-programmable plastic) CMOS EPROM (UV-erasable)
Package 28-pin PLCC (J-lead) 24-pin CERDIP / PDIP
Operating Temperature Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] 0 C to +70 C (commercial) / -55 C to +125 C (military)
Speed Grade -35 (slowest EP610) β€”
Mounting Type Surface Mount Through-Hole
Programmable Pins 24 input / 16 output (shared macrocells) β€”
RoHS Status [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead_free] β€”
MSL Level [DATA_NEEDED: msl_level] β€”
Programming Tool MAX+PLUS II development system β€”
Macro Cells β€” 16
Logic Gates β€” Equivalent to 300 gates (typical)
Pin-to-Pin Delay (tPD) β€” 30 ns
Pipelined Data Rate β€” up to 100 MHz
Supply Voltage (VCC) β€” 4.75 V to 5.25 V
Programming Voltage (VPP) β€” 13 V nominal
Erase/Program Cycles β€” 1000 typical
Output Type β€” CMOS tri-state (programmable)
Logic Compatibility β€” TTL and CMOS
Turbo Mode β€” Yes (registered path bypass)

Datasheets & Resources

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