EP610LC-35 - 16-Macrocell Classic EPLD, 37ns, 5V, PLCC-35 | Altera
MPN: EP610LC-35 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EP610LC-35 Overview
A Classic EPLD is a non-volatile programmable logic device that combines the integration of a PLD with erasable CMOS architecture, sitting in the hierarchy between discrete 22V10-style SPLDs and modern SRAM-based FPGAs. The EP610 family targets glue-logic replacement, state-machine implementation, and decoder/encoder functions in 5 V systems where a small number of logic functions must be implemented in a single package.
Key features include 24 dedicated input pins, 16 output macrocells, 4 combinatorial feedback paths per macrocell, programmable I/O architecture, and a synchronous prescaler for flexible clock division. The Classic family supports 100% factory-tested AC and DC specifications with on-board logic-test circuitry that enables standard production-flow verification. Macrocells share a sum term and product term, allowing wide-input AND/OR functions to be combined with registered outputs.
The EP610 uses CMOS EEPROM-based configuration cells backed by UV-erasable windowed ceramic variants (EP610I/J) and one-time-programmable plastic variants (EP610L/D). Architecture-wise, every macrocell contains a flip-flop, an output enable, and feedback into the AND-array, supporting both registered and combinatorial outputs from the same physical pin. The 37 ns tpd speed grade (-35) is the slowest of the EP610 family and trades timing margin for slightly lower dynamic current draw at lower toggle rates.
Typical applications include 5 V bus decoding, address mapping for microcontroller and 8-bit/16-bit processor systems, state-machine controllers, glue-logic consolidation in industrial control boards, and replacement of legacy 22V10 PAL/GAL devices. The wide supply tolerance makes it usable in 5 V-only industrial backplanes where modern 3.3 V-only CPLDs are not pin-compatible.
When designing with this part, note that the -35 speed grade is the slowest EP610 variant; verify timing margins carefully when porting -25 or -15 designs. Programming is performed via the Altera MAX+PLUS II development system and a hardware programmer; source files are still maintained in the Altera Classic Device Family support archive.
This page synthesizes distributor pricing, Rochester Electronics stock status, same-family speed-grade and package alternatives, and practical design notes that go beyond the marketing blurb in the original datasheet.
Drop-in alternatives for EP610LC-35 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610LC-35 (same form factor and footprint) — differing in Package, Family, Operating Temperature, Technology, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610LC-30
✅ Drop-In✓ In Stock
$16.4 / Unit
View Datasheet →EP610LC-25
✅ Drop-In✓ In Stock
$6.2 / Unit
View Datasheet →EP610LC-15
✅ Drop-In✓ In Stock
$4.65 / Unit
View Datasheet →EP610ILC-35
✅ Drop-In📋 Reference alternative (not in catalog)
EP610JI-30
✅ Drop-In✓ In Stock
$9.4 / Unit
View Datasheet →EP610LC-35 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Device Series | EP610 |
| Macrocells | 16 |
| Usable Gates | 300 |
| Propagation Delay (tpd) | 37 ns |
| Supply Voltage (Vcc) | 5 V |
| Technology | CMOS EEPROM (one-time-programmable plastic) |
| Package | 28-pin PLCC (J-lead) |
| Speed Grade | -35 (slowest EP610) |
| Mounting Type | Surface Mount |
| Programmable Pins | 24 input / 16 output (shared macrocells) |
| Programming Tool | MAX+PLUS II development system |
EP610LC-35 Pin Configuration
| Pin 1 | I/O — Macrocells input/output shared with input array |
| Pin 2 | I/O — Macrocells input/output shared with input array |
| Pin 3 | INPUT — Dedicated input to AND-array |
| Pin 4 | INPUT — Dedicated input to AND-array |
| Pin 5 | INPUT — Dedicated input to AND-array |
| Pin 6 | INPUT — Dedicated input to AND-array |
| Pin 7 | INPUT — Dedicated input to AND-array |
| Pin 8 | INPUT — Dedicated input to AND-array |
| Pin 9 | INPUT — Dedicated input to AND-array |
| Pin 10 | GND — Ground |
| Pin 11 | INPUT — Dedicated input to AND-array |
| Pin 12 | INPUT — Dedicated input to AND-array |
| Pin 13 | I/O — Macrocells input/output shared with input array |
| Pin 14 | I/O — Macrocells input/output shared with input array |
| Pin 15 | I/O — Macrocells input/output shared with input array |
| Pin 16 | I/O — Macrocells input/output shared with input array |
| Pin 17 | I/O — Macrocells input/output shared with input array |
| Pin 18 | I/O — Macrocells input/output shared with input array |
| Pin 19 | I/O — Macrocells input/output shared with input array |
| Pin 20 | VCC — 5 V supply voltage |
| Pin 21 | I/O — Macrocells input/output shared with input array |
| Pin 22 | I/O — Macrocells input/output shared with input array |
| Pin 23 | INPUT — Dedicated input to AND-array |
| Pin 24 | INPUT — Dedicated input to AND-array |
| Pin 25 | INPUT — Dedicated input to AND-array |
| Pin 26 | INPUT — Dedicated input to AND-array |
| Pin 27 | INPUT — Dedicated input to AND-array |
| Pin 28 | INPUT — Dedicated input to AND-array |
Typical Applications
EP610LC-35 is suitable for 6 applications: 5 V Bus Address Decoding, Glue Logic Consolidation, State-Machine Controllers, Legacy 22V10 PAL/GAL Replacement, Industrial Control Board I/O Expansion, Retro Computing and Hobby Projects.
5 V Bus Address Decoding
The EP610LC-35 is well suited for 5 V address decoding in 8-bit and 16-bit microcontroller or microprocessor systems where modern 3.3 V CPLDs are not pin-compatible. With 16 macrocells and 24 inputs, it can implement multiple chip-select decode functions for memory and peripheral banks, replacing two or three discrete 22V10 PAL/GAL devices on a legacy ISA, PC/104, or STD-bus backplane. The 37 ns tpd adds a small but acceptable decode delay for asynchronous bus cycles, while the 5 V CMOS supply directly interfaces with TTL logic without level shifters. Designers should budget one macrocell per chip-select and consolidate wide-AND gating through the shared product-term array to minimize macrocell count.
Recommended
Glue Logic Consolidation
The EP610LC-35 consolidates discrete 74LS/74HC glue logic such as latches, multiplexers, and shift registers into a single programmable device on industrial 5 V backplanes. With 16 macrocells and full feedback, designers can replace five to ten discrete packages, reducing board area and improving noise immunity through shorter signal paths. The single 5 V CMOS supply and TTL-compatible I/O make it a direct drop-in for 74LS logic replacement. A typical migration converts a board's discrete gates into one EP610LC, two bypass capacitors, and a single 28-pin PLCC footprint, often yielding BOM savings and improved reliability.
Recommended
State-Machine Controllers
The EP610LC-35 implements small to medium state machines such as motor-control sequencers, printer-paper-feed controllers, or vending-machine dispense logic in a single 28-pin PLCC. Each macrocell's flip-flop, combined with shared product terms, supports Moore and Mealy state machines with up to 16 states and rich next-state branching. The 37 ns clock-to-output adds a deterministic propagation delay suitable for stepper-motor pulse trains, solenoid timing, and human-perceptible mechanical sequencing. Design entry uses MAX+PLUS II state-machine syntax with AHDL or VHDL, and the resulting JEDEC file programs directly into the device via a hardware programmer.
Recommended
Legacy 22V10 PAL/GAL Replacement
The EP610LC-35 directly replaces legacy 22V10 PAL and GAL devices in designs that need additional macrocells or extra inputs while remaining on a 5 V CMOS supply. With 16 macrocells versus the 22V10's 10, the EP610 implements equivalent sum-of-products logic with more output flexibility, including per-pin registered/combinatorial mode and feedback. It accepts industry-standard JEDEC files generated for the 22V10 footprint after minor pin remapping, and is widely used in industrial controller board respins where the original 22V10 design files are no longer supported by modern tools. Rochester Electronics sustains both EP610LC and 22V10 supply for these legacy platforms.
Recommended
Industrial Control Board I/O Expansion
The EP610LC-35 expands I/O in industrial PLC and process-control boards by combining input debouncing, output pulse-stretching, and watchdog logic into one device on a 5 V backplane. The 24 dedicated inputs handle multiple switch and sensor lines with on-chip debounce implemented as counters in the macrocell array, while the 16 macrocell outputs drive optocouplers, relays, or 24 V signal-conditioning stages through external drivers. The 37 ns tpd is fast enough for sub-millisecond I/O scan times typical of PLC scan architectures. The plastic PLCC package withstands industrial-vibration environments when socketed in a machined-pin PLCC socket.
Recommended
Retro Computing and Hobby Projects
The EP610LC-35 is popular in retro-computing hobby projects such as Apple II, TRS-80, CP/M, and early IBM-PC peripheral boards where 5 V CMOS logic and a PLCC-friendly socket simplify build versus original 24-pin or 28-pin DIP PLDs. With JEDEC files downloadable from retro hardware archives, hobbyists can re-create working chips for broken vintage machines, using a TL866 or compatible programmer with legacy EP610 support. The 37 ns speed grade provides generous timing margin for the bus cycles of 1 MHz 6502, Z80, and 8088-era processors. Single-unit pricing through Rochester Electronics makes small-quantity restoration feasible.
Recommended
Recommended Products Summary
Engineering reference data for EP610LC-35 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610LC-30 | EP610LC-25 | EP610LC-15 | EP610ILC-35 | EP610JI-30 |
|---|---|---|---|---|---|---|
| Package | 28-pin PLCC (J-lead) | 28-pin PLCC (J-lead) - same | 28-pin PLCC (J-lead) - same | 28-pin PLCC (J-lead) - same | 28-pin PLCC (J-lead) - same | 28-pin PLCC (J-lead) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tpd) | 37 ns | 30 ns | 25 ns | 15 ns | 37 ns | 30 ns |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 300 | 300 | 300 | 300 | 300 | 300 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Range | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Military (extended) |
| Technology | CMOS EEPROM (OTP plastic) | CMOS EEPROM (OTP plastic) | CMOS EEPROM (OTP plastic) | CMOS EEPROM (OTP plastic) | CMOS EEPROM (OTP plastic) | CMOS EPROM (ceramic windowed) |
Key Differentiators
- Slowest speed grade in EP610 family for cost-sensitive designs (vs EP610LC-25)
- Plastic J-lead chip carrier for surface-mount assembly (vs EP610PC-35 (PDIP))
- One-time-programmable CMOS EEPROM cells for low cost (vs EP610JI-30 (windowed ceramic))
Design Notes
The -35 speed grade is the slowest EP610 variant at 37 ns tpd. Designs ported from the -25 or -15 grade must re-check setup and hold margins because the slower grade adds up to 22 ns of additional delay on critical paths. Always run post-route timing simulation in MAX+PLUS II after downgrading the speed grade to verify system-level timing closure.
Place a 0.1 uF decoupling capacitor as close as possible to the VCC pin (pin 20) and a bulk 10 uF tantalum capacitor on the same 5 V rail within 25 mm of the device. The PLCC socket should be a machined-pin type (not stamped) for reliable contact, particularly in industrial-vibration environments. Reserve PLCC extraction tool access around the socket footprint.
Route all input-only pins (3-9, 11-12, 23-28) with short traces to minimize input loading on the AND-array. Keep clock inputs (any pin assigned as a clock) routed away from high-di/dt signals such as relay coils or switching power converters. The Classic EPLD has no internal PLL, so clock skew must be managed externally via matched trace lengths for multi-EPLD designs.
Estimated: at 5 V VCC and 25 MHz toggle rate across all 16 macrocells, the EP610LC-35 draws approximately 60-90 mA of dynamic supply current with all outputs switching CMOS loads. Add 20% margin for the I/O switching current, giving a typical design budget of 110 mA. The device has no internal power-on reset; the first clock edge after VCC stable must be clean, or use an external POR circuit for state-machine startup integrity.
Compliance Information
EP610 family predates RoHS compliance; the EP610LC-35 (plastic, 1990s-era) was originally specified for standard Pb-bearing solder. Modern RoHS-compliant variants require Rochester Electronics' lead-free reballing service. AEC-Q100 not applicable for legacy plastic EPLDs. Verify current RoHS status with Rochester Electronics at order entry.
