EP610LI-35 vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610LI-35 by Altera and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LI-35 | EP610DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.50 | $18.40 |
| Family | Classic EPLD | Altera Classic EP610 |
| Series | EP610 | β |
| Number of Macrocells | 16 | β |
| Usable Gates | 300 | 300 |
| Number of I/O Pins | 16 | β |
| Total Inputs | 20 | β |
| Dedicated Inputs | 4 | β |
| External Clock Inputs | 2 | β |
| Product Terms | 160 | β |
| Maximum Propagation Delay | 35 ns (tpd) | β |
| Maximum Operating Frequency | 28.6 MHz (fmax) | β |
| Pipelined Data Rate | Up to 100 MHz | up to 100 MHz |
| Supply Voltage | 5 V | β |
| Process Technology | CMOS | CMOS |
| Architecture | PAL-type (AND-OR array) | β |
| Package | 28-pin PLCC (windowed ceramic, 'LI') | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Operating Temperature Range | [DATA_NEEDED: military/industrial operating temperature range] | β |
| Programming Technology | UV-erasable (EPROM) | β |
| Mounting Type | Surface Mount | Through-Hole (DIP) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | β | CPLD - Classic EPLD |
| Macrocells | β | 16 |
| Propagation Delay (tPD) | β | 35 ns |
| Maximum Frequency (fMAX) | β | 28.6 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Program/erase Method | β | UV-erasable (windowed CERDIP) |
| Operating Temperature | β | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Manufacturer | β | Originally Altera; today supplied via Rochester Electronics (authorized) |