EP610PC-15 vs EP610DC-15 Comparison
Detailed side-by-side comparison of EP610PC-15 by Altera and EP610DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-15 | EP610DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.50 | $7.95 |
| Family | Classic EPLD | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Usable Gates | 300 gates | β |
| Macrocells | 16 | 16 |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | β |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | β |
| Pipelined Data Rate | Up to 100 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V |
| Technology | CMOS | CMOS |
| Architecture | PAL-type, sum-of-products AND/OR array | UV-erasable CMOS PAL-type |
| TTL Emulation | 100% TTL compatible | β |
| Package | PDIP-24 (plastic DIP, 24-pin) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Pin Count | 24 pins | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to 70C (commercial) |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Development Tool | Altera MAX+PLUS II | β |
| Logic Test Circuitry | On-board for AC/DC verification | β |
| Product Family | β | Classic EPLD (EP610) |
| Logic Expanders | β | 4 |
| Dedicated Inputs | β | 20 |
| Bidirectional I/O Pins | β | 16 |
| Total Product Terms | β | 160 |
| Propagation Delay (tPD) | β | 15 ns (speed grade -15) |
| Maximum Internal Clock Frequency | β | 71.4 MHz |
| Programming Method | β | JEDEC fuse map, UV erasure |