EP610PC-15 - 16-Macrocell Classic EPLD, 15ns PDIP-24 | Altera
MPN: EP610PC-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.31 | $28.31 |
| 10 | $25.48 | $254.80 |
| 100 | $22.65 | $2,265.00 |
| 500 | $19.82 | $9,910.00 |
| 1,000 | $17.5 | $17,500.00 |
EP610PC-15 Overview
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that combines the architectural simplicity of PAL/GAL devices with higher gate density and on-chip macrocell registers. Within the broader taxonomy, the EP610 belongs to the chain: EPLD -> CPLD -> Programmable Logic Device (PLD) -> Logic IC -> Integrated Circuit. Classic EPLDs are CMOS UV-erasable parts historically used to replace multiple discrete PAL/GAL chips with a single, in-system reconfigurable device, sitting upstream of the FPGA family in the programmable-logic evolution.
Key features of the EP610PC-15 include 100% TTL emulation, on-board logic test circuitry for AC/DC verification during production flow, integrated macrocell flip-flops, and a choice of speed grades (-15, -20, -25, -30, -35) with the -15 being the slowest variant. The Classic family supports 300 to 900 usable gates, but the EP610 specifically targets the 16-macrocell / 300-gate entry point for low-density glue logic. It is a PAL-type architecture with CMOS technology and a 17 ns tPD (per Datasheets360 listing).
The device architecture is based on a sum-of-products PLA-style AND/OR array feeding 16 macrocells, each with a programmable flip-flop and I/O control. This makes the EP610PC-15 well-suited to state-machine, address-decoding, and bus-arbitration functions where non-volatility, deterministic timing, and a simple development toolchain (MAX+PLUS II) are valued.
Typical applications include address decoding in 8086/68k/MIPS-based systems, glue logic between microprocessors and peripherals, bus arbitration, state-machine controllers, and legacy industrial control replacement where original Altera Classic parts must be form-fit-function substitutes. Because the EP610 is in production through Rochester Electronics as a long-life sustaining product, it continues to be specified for EOL (end-of-life) boards and long-lifecycle aerospace/defense programs.
When designing with this device, note that the 15ns grade has the slowest tPD in the family - if your timing budget is tight, choose -20, -25, -30, or -35 instead. Verify the supply voltage (5V only) and the package footprint (24-pin PDIP, 0.3 inch row spacing) match the legacy PCB layout before substitution.
This page synthesizes Rochester Electronics distributor pricing, same-family drop-in alternatives, and design notes not found in the original Altera datasheet, providing practical sourcing intelligence for engineers maintaining legacy EPLD designs.
Drop-in alternatives for EP610PC-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610PC-15 (same form factor and footprint) β differing in Package, Supply Voltage (VCC), Operating Temperature, Programming Method, Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP610PC-20
β Drop-Inβ In Stock
$47.8 / Unit
View Datasheet βEP610PC-25
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEP610PC-30
β Drop-Inβ In Stock
$27.74 / Unit
View Datasheet βEP610DC-15
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEP610DC-25
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP610JI-30
β Drop-Inβ In Stock
$9.4 / Unit
View Datasheet βEP610PC-15T
β Drop-Inπ Reference alternative (not in catalog)
EP610PC-15 Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 300 gates |
| Macrocells | 16 |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | 100 MHz (per family datasheet) |
| Pipelined Data Rate | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V (single supply) |
| Technology | CMOS |
| Architecture | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | 100% TTL compatible |
| Package | PDIP-24 (plastic DIP, 24-pin) |
| Pin Count | 24 pins |
| Mounting Type | Through-Hole (DIP) |
| Development Tool | Altera MAX+PLUS II |
| Logic Test Circuitry | On-board for AC/DC verification |
EP610PC-15 Pin Configuration
| Pin 1 | I/O β User I/O / macrocell input-output |
| Pin 2 | I/O β User I/O / macrocell input-output |
| Pin 3 | I/O β User I/O / macrocell input-output |
| Pin 4 | I/O β User I/O / macrocell input-output |
| Pin 5 | I/O β User I/O / macrocell input-output |
| Pin 6 | I/O β User I/O / macrocell input-output |
| Pin 7 | I/O β User I/O / macrocell input-output |
| Pin 8 | I/O β User I/O / macrocell input-output |
| Pin 9 | I/O β User I/O / macrocell input-output |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β User I/O / macrocell input-output |
| Pin 12 | I/O β User I/O / macrocell input-output |
| Pin 13 | I/O β User I/O / macrocell input-output |
| Pin 14 | I/O β User I/O / macrocell input-output |
| Pin 15 | I/O β User I/O / macrocell input-output |
| Pin 16 | I/O β User I/O / macrocell input-output |
| Pin 17 | I/O β User I/O / macrocell input-output |
| Pin 18 | I/O β User I/O / macrocell input-output |
| Pin 19 | I/O β User I/O / macrocell input-output |
| Pin 20 | VCC β +5V supply |
| Pin 21 | I/O β User I/O / macrocell input-output |
| Pin 22 | I/O β User I/O / macrocell input-output |
| Pin 23 | I/O β User I/O / macrocell input-output |
| Pin 24 | I/O β User I/O / macrocell input-output |
Typical Applications
EP610PC-15 is suitable for 6 applications: Microprocessor Address Decoding, Glue Logic Consolidation, Bus Arbitration and Control, State Machine Controllers, Legacy Industrial Control Replacement, Board-Test and JTAG Bridge Logic.
Microprocessor Address Decoding
The EP610PC-15's 16 macrocells and 300 usable gates provide exactly the logic capacity needed for address decoding in legacy 8-bit and 16-bit microprocessor systems such as 8086, 68k, and Z80-based designs. Its non-volatile CMOS technology means the decode map is retained without external boot memory, and the 15ns tPD fits well within typical memory-access cycle times where the address bus must be decoded before chip-select assertions. Compared to discrete 74LS-series decoder logic, a single EP610PC-15 replaces several decoder packages and allows late-stage PCB rework via reprogramming, accelerating prototyping. The 5V supply matches TTL-era microprocessor rails directly, eliminating level-shifter overhead, while the 24-pin PDIP footprint drops into standard through-hole legacy PCBs without redesign.
Recommended
Glue Logic Consolidation
Designers historically replaced arrays of 74LS, 74HC, and PAL/GAL chips with a single EP610PC-15 to consolidate random glue logic in industrial controllers, telecom backplanes, and instrumentation. The Classic EPLD's PAL-type sum-of-products architecture maps naturally to glue-logic equations, and 16 macrocells handle typical 4-to-6 chip-select, interrupt-priority, and bus-arbitration tasks. The 100% TTL compatibility ensures direct interfacing with legacy 5V logic families without buffering, while the on-board logic test circuitry allows AC/DC verification during production flow. Compared to multiple discrete SSI/MSI packages, the EP610PC-15 reduces board area, lowers power, and simplifies BOM management - a key reason Rochester Electronics continues to sustain this part for long-lifecycle programs.
Recommended
Bus Arbitration and Control
Multi-master bus systems such as ISA, VME, and proprietary backplanes require deterministic, fast arbitration logic - exactly the role the EP610PC-15 was designed to fill. Its 15ns pin-to-pin tPD enables sub-30ns arbitration latency, and the macrocell flip-flops latch grant signals with predictable clock-to-out timing. The Classic EPLD's 5V CMOS design interfaces directly with TTL bus transceivers, while the 16 macrocells support 4-to-8 master arbitration trees with parity and timeout logic. Compared to discrete TTL arbiters, the EP610PC-15 allows protocol updates via reprogramming rather than board rework, a major advantage for field-upgradable industrial systems. Sustained availability through Rochester Electronics makes it a reliable choice for legacy aerospace and defense bus systems still in service.
Recommended
State Machine Controllers
The EP610PC-15 is well-suited to implementing finite-state machines for protocol converters, sequence controllers, and test equipment front panels where Moore or Mealy state machines need 8-to-16 states with deterministic transitions. Each macrocell's flip-flop plus the AND/OR product-term array maps directly to standard FSM synthesis, and the 100 MHz counter frequency supports high-speed protocol bit timing. The non-volatile CMOS process means state tables survive power cycles without external storage, while MAX+PLUS II development flow accepts VHDL/Verilog/AHDL or schematic state-diagram entry. Compared to microcontrollers, the EP610PC-15 offers sub-microsecond deterministic response with no firmware boot delay, an advantage for safety interlocks and machine-control loops.
Recommended
Legacy Industrial Control Replacement
Industrial control systems installed in the 1990s and 2000s often integrate Altera Classic EPLDs as control-logic cores, and the EP610PC-15 specifically appears in PLC backplanes, motor-drive gate controllers, and SCADA remote-terminal units. With the original Altera fab line closed, Rochester Electronics is the authorized sustaining manufacturer, providing form-fit-function replacements that match the original 24-pin PDIP footprint and JEDEC fuse file. Engineers maintaining these long-lifecycle systems rely on the EP610PC-15 for spare-part replenishment and EOL board repair rather than redesigning to modern CPLDs. Compared to unauthorized clones, Rochester Electronics parts carry original Altera IP and are guaranteed bit-compatible with legacy MAX+PLUS II JEDEC files, eliminating revalidation cost.
Recommended
Board-Test and JTAG Bridge Logic
The EP610PC-15's on-board logic test circuitry - documented in the Classic EPLD family datasheet - allows verification of function and AC specifications during standard production flow, making it valuable as a built-in self-test (BIST) controller or JTAG bridge on legacy boards. Its 16 macrocells handle typical boundary-scan register coordination, and the 15ns tPD keeps test-clock timing within IEEE 1149.1 specifications. The 5V CMOS I/O interfaces with classic JTAG chain drivers, while the 24-pin PDIP footprint fits standard through-hole test fixtures. Compared to dedicated JTAG controllers, an EP610PC-15 combines test logic with general glue logic, reducing component count on legacy test-and-measurement boards where every square inch of PCB counts.
Recommended
Recommended Products Summary
Engineering reference data for EP610PC-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610PC-20 | EP610PC-25 | EP610PC-30 | EP610DC-15 | EP610JI-30 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PDIP-24 | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 300 | 300 | 300 | 300 | 300 | 300 |
| Pin-to-Pin Delay (tPD) | 15 ns | 20 ns | 25 ns | 30 ns | 15 ns | 30 ns |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Maximum Counter Frequency | 100 MHz | 100 MHz | 83.3 MHz | 83.3 MHz | 100 MHz | 83.3 MHz |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Commercial | Industrial |
| Lifecycle Status | NRND (sustained by Rochester) | NRND (sustained by Rochester) | NRND (sustained by Rochester) | NRND (sustained by Rochester) | NRND (sustained by Rochester) | NRND (sustained by Rochester) |
Key Differentiators
- Slowest speed grade in the EP610 family - allows lower-cost legacy timing budgets (vs EP610PC-35)
- Commercial temperature grade in PDIP through-hole package (vs EP610JI-30)
- Rochester Electronics sustaining manufacture - guaranteed long-term supply (vs EP610PC-15T)
Design Notes
The EP610PC-15 operates from a single 5V supply. Decouple VCC (pin 20) with a 0.1uF ceramic capacitor placed within 5mm of the supply pin, plus a 10uF tantalum or aluminum bulk capacitor on the same rail. The Classic EPLD has TTL-compatible inputs that can float to logic-high if left unconnected, but unused outputs should be left open or terminated per board-level requirements to minimize crosstalk. Avoid sharing the EP610PC-15's 5V rail with high-current switching regulators - the part's 100% TTL compatibility makes it susceptible to supply noise that could induce metastability in macrocell flip-flops.
Do not confuse the EP610PC-15 (16 macrocells, 300 gates) with the larger EP910 (24 macrocells, 900 gates) or EP1810 (48 macrocells, 1800 gates) - all share a similar naming scheme but differ in logic capacity. The 'PC' suffix indicates PDIP-24 plastic package with commercial temperature grade; 'DC' is also PDIP-24 commercial, 'DM' is CerDIP military, 'JI' is PLCC industrial. When substituting, verify both the macrocell count and the package code match the original design. Substituting an EP610 into an EP910 socket will leave logic unimplemented, while substituting an EP910 into an EP610 socket wastes capacity but functions electrically.
The 24-pin PDIP package has 0.1 inch (2.54mm) pin pitch and standard 0.3 inch row spacing. Route all signal traces on the solder side or use a socket for programming convenience. Keep programming-pin traces short to minimize noise coupling during JEDEC file loading. For mixed-logic boards (5V EP610 alongside 3.3V microcontrollers), use a level translator such as 74LVC245 on the 3.3V-to-5V direction; the EP610PC-15 does not tolerate 3.3V inputs as logic-high reliably. Maintain ground-plane integrity under the device to control switching noise from the macrocell flip-flops.
Compliance Information
Operating temperature and RoHS status not explicitly stated in the Verified Web Data; marked [DATA_NEEDED] in specs. Classic EPLDs from this era were typically built in leaded PDIP packages - lead-free status is unknown for the original Altera part. Rochester Electronics as the current manufacturer follows modern compliance standards, but specific certificates should be requested from the supplier.
