EP610PC-20 vs EP610DC-20 Comparison
Detailed side-by-side comparison of EP610PC-20 by Altera and EP610DC-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-20 | EP610DC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $47.80 | $15.85 |
| Family | Classic EPLD | Classic EP610 |
| Logic Elements | 16 macrocells | β |
| Usable Gates | 300 | β |
| Propagation Delay (tPD) | 20 ns | 22 ns |
| Maximum Operating Frequency | 100 MHz (pipelined) | β |
| Supply Voltage (VCC) | 5 V Β±10% | 4.75 V to 5.25 V (5 V nominal) |
| Number of Pins | 24 | β |
| Package | PDIP-24 | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Operating Temperature | 0C to +70C (commercial) | 0 Β°C to 70 Β°C (commercial) |
| Process Technology | CMOS EPROM | CMOS, UV-erasable floating gate |
| Programmable Flip-Flops | 16 | β |
| Input Pins | 24 | β |
| Output Pins | 16 | β |
| I/O Compatibility | TTL | β |
| Program/Erase Method | UV (windowed) or OTP | β |
| RoHS Status | Non-compliant (legacy PDIP) | [DATA_NEEDED: RoHS compliance status] |
| Product Type | β | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Logic Macrocells | β | 16 |
| Dedicated Inputs | β | 4 |
| I/O Pins | β | 16 (bidirectional) |
| Total Usable Pins | β | 20 |
| Product Terms (p-terms) | β | 160 |
| Maximum Toggle Frequency (fMAX) | β | 55.6 MHz |
| Programming Method | β | UV erasure + parallel programmer |
| Mounting Type | β | Through-hole |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |