EP610PC-20 - Classic EPLD, 16 Macrocells, 100 MHz | Altera
MPN: EP610PC-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $72.85 | $72.85 |
| 10 | $65.5 | $655.00 |
| 100 | $58.2 | $5,820.00 |
| 500 | $52.4 | $26,200.00 |
| 1,000 | $47.8 | $47,800.00 |
EP610PC-20 Overview
A Classic EPLD is a type of programmable logic device that combines the non-volatility and instant-on behavior of EPROM with the flexibility of combinatorial and sequential logic implementation. In the system hierarchy, an EPLD sits between simple PLDs (PAL/GAL) and modern CPLDs/FPGAs, providing predictable timing, deterministic propagation delay, and a small macrocell count optimized for fast logic integration. The EP610 was Altera's second-generation Classic EPLD, designed for high-speed decoder, counter, and bus-interface applications where bipolar PALs lacked speed or density.
Key features of the EP610PC-20 include 16 macrocells, 24 dedicated input pins, 16 flip-flops with individual clear/preset control, programmable output polarity, and a 5 V ±10% single-supply operation. The device offers 100 MHz registered operation, 20 ns tPD (commercial grade), and a maximum I/O count consistent with the 24-pin PDIP footprint. The architecture is a sum-of-products array feeding 16 macrocells, with each macrocell containing a programmable flip-flop and output enable logic, allowing implementation of either combinatorial or registered logic functions.
Architecturally, the EP610 uses a unified AND/OR array with a fixed internal interconnect, eliminating the routing variability of FPGAs. The CMOS EPROM process provides zero standby power and full TTL compatibility, while the deterministic tPD enables accurate timing analysis without static timing closure tools. Compared to bipolar 20 ns PALs, the EP610PC-20 adds programmability of registered outputs and eliminates the need for separate PAL/flip-flop pairs on a board.
Typical applications include bus decoders and address-mapping logic in 8086/68000-era microprocessor systems, high-speed glue logic between ASICs and standard peripherals, replacement of multiple 20 ns PALs with a single device, DMA state machines, interrupt controllers, and legacy industrial control designs. The 100 MHz pipelined throughput also makes the device useful for frequency-division and clock-distribution networks.
When designing with the EP610PC-20, ensure that the 5 V supply is within ±10% tolerance, place a 0.1 µF decoupling capacitor near each VCC pin, and confirm that the device programmer supports the Classic EPLD algorithm (e.g., Data I/O, BP-1200, or equivalent). For production, use the one-time-programmable (OTP) windowless variant if UV erasure is not required, and program the security bit to prevent pattern readback.
This page synthesizes distributor pricing from Rochester Electronics and authorized resellers, same-family drop-in alternatives (EP610PC-15, EP610LC-25, EP610DC-25) from the Site MPN list, and practical design notes not found in the original manufacturer datasheet.
Drop-in alternatives for EP610PC-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610PC-20 (same form factor and footprint) — differing in Package, Supply Voltage (VCC), Propagation Delay (tPD), Operating Temperature, Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610PC-15
✅ Drop-In✓ In Stock
$17.5 / Unit
View Datasheet →EP610DC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610DC-20
✅ Drop-In✓ In Stock
$15.85 / Unit
View Datasheet →EP610DC-15
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EP610PC-20T
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EP610PC-20 Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD |
| Logic Elements | 16 macrocells |
| Usable Gates | 300 |
| Propagation Delay (tPD) | 20 ns |
| Maximum Operating Frequency | 100 MHz (pipelined) |
| Supply Voltage (VCC) | 5 V ±10% |
| Number of Pins | 24 |
| Package | PDIP-24 |
| Operating Temperature | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM |
| Programmable Flip-Flops | 16 |
| Input Pins | 24 |
| Output Pins | 16 |
| I/O Compatibility | TTL |
| Program/Erase Method | UV (windowed) or OTP |
| RoHS Status | Non-compliant (legacy PDIP) |
EP610PC-20 Pin Configuration
| Pin 1 | I/O0 — Bidirectional I/O / macrocell output 0 |
| Pin 2 | I/O1 — Bidirectional I/O / macrocell output 1 |
| Pin 3 | I/O2 — Bidirectional I/O / macrocell output 2 |
| Pin 4 | I/O3 — Bidirectional I/O / macrocell output 3 |
| Pin 5 | I/O4 — Bidirectional I/O / macrocell output 4 |
| Pin 6 | I/O5 — Bidirectional I/O / macrocell output 5 |
| Pin 7 | I/O6 — Bidirectional I/O / macrocell output 6 |
| Pin 8 | I/O7 — Bidirectional I/O / macrocell output 7 |
| Pin 9 | I/O8 — Bidirectional I/O / macrocell output 8 |
| Pin 10 | GND — Ground |
| Pin 11 | I/O9 — Bidirectional I/O / macrocell output 9 |
| Pin 12 | I/O10 — Bidirectional I/O / macrocell output 10 |
| Pin 13 | I/O11 — Bidirectional I/O / macrocell output 11 |
| Pin 14 | I/O12 — Bidirectional I/O / macrocell output 12 |
| Pin 15 | I/O13 — Bidirectional I/O / macrocell output 13 |
| Pin 16 | I/O14 — Bidirectional I/O / macrocell output 14 |
| Pin 17 | I/O15 — Bidirectional I/O / macrocell output 15 |
| Pin 18 | IN0 — Dedicated input 0 |
| Pin 19 | IN1 — Dedicated input 1 |
| Pin 20 | IN2 — Dedicated input 2 |
| Pin 21 | OE — Output Enable (active low) |
| Pin 22 | VCC — +5 V supply |
| Pin 23 | CLK — Clock input for macrocell flip-flops |
| Pin 24 | CLR — Master clear / register reset |
Typical Applications
EP610PC-20 is suitable for 6 applications: Microprocessor Bus Decoder, DMA State Machine Controller, Interrupt Controller Glue Logic, High-Speed Frequency Divider / Clock Distribution, Legacy Industrial Control Replacement, Multi-PAL Consolidation (Glue Logic Replacement).
Microprocessor Bus Decoder
The EP610PC-20's 16 macrocells, 20 ns tPD, and 24 dedicated inputs make it ideal for 8086/68000 bus decoder applications. Engineers typically use the device to decode address lines, chip-select signals, and memory-mapped I/O regions previously implemented with multiple 20 ns bipolar PALs. The 100 MHz pipelined throughput allows the EPLD to drive bus arbitration logic at full CPU clock without wait states. Place the EPLD between the address bus and the peripheral CS pins; configure macrocells to implement the combinatorial decode equations. The 5 V TTL-compatible I/O eliminates level-shifters on legacy motherboards. Compared to discrete PAL/flip-flop pairs, the EP610PC-20 consolidates decoder + register logic into one package, reducing board area by 40-60% and improving timing predictability through the device's deterministic tPD.
Recommended
DMA State Machine Controller
The EP610PC-20's 16 programmable flip-flops and sum-of-products array provide an optimal platform for implementing DMA transfer state machines. With 20 ns tPD and 100 MHz pipelined rates, the device can sequence HOLD/HLDA handshakes, address generation, and transfer-count termination for ISA or VME bus architectures. Each macrocell's individual clear/preset control simplifies the implementation of multi-state controllers where some flip-flops must reset on entry to specific states. The CMOS EPROM technology provides zero standby power, critical for battery-backed industrial systems. Engineers can program the EPLD once and benefit from instant-on behavior at power-up, unlike SRAM-based FPGAs that require configuration time.
Recommended
Interrupt Controller Glue Logic
In legacy 8086/286-era interrupt controllers, the EP610PC-20 provides the prioritization, masking, and vector-generation glue logic that typically surrounded a master 8259A PIC. The 16 macrocells can implement up to 16 priority-encoded interrupt sources with individual mask bits, and the 20 ns tPD ensures interrupt acknowledge latency stays within one CPU clock cycle. The TTL-compatible I/O integrates directly with the 8259A's control bus without external buffers. The deterministic propagation delay is a key advantage over FPGAs in this role, because interrupt latency must be bounded and predictable in real-time control systems.
Recommended
High-Speed Frequency Divider / Clock Distribution
The 100 MHz pipelined throughput of the EP610PC-20 makes it useful for binary and decade frequency dividers used in clock-distribution networks. With 16 flip-flops and combinatorial feedback paths, a single EPLD can implement multi-stage dividers previously requiring several 74LS161/163 counters. The 20 ns tPD ensures divider propagation delays stay well below the input clock period up to 50 MHz. The 5 V supply and TTL I/O are compatible with legacy 74-series logic families, allowing direct insertion into existing clock trees without level translation.
Recommended
Legacy Industrial Control Replacement
The EP610PC-20's instant-on CMOS EPROM technology makes it ideal for legacy industrial control systems that must start operating the moment power is applied, without FPGA configuration delay. Common applications include PLC ladder-logic replacement, motor-control timing sequencers, and safety-interlock logic. The device operates from 0C to +70C and tolerates the 5 V ±10% supply commonly found in factory-floor power systems. The PDIP-24 package is also mechanically robust for vibration-prone industrial environments. For military and aerospace extensions, the same 24-pin DIP footprint in the EP610DC-25 ceramic variant provides -55C to +125C operation.
Recommended
Multi-PAL Consolidation (Glue Logic Replacement)
The EP610PC-20's 16 macrocells and 24 inputs can replace 3-5 standard 20-pin bipolar PALs in legacy designs where board area and power consumption are constraints. The CMOS EPROM process reduces quiescent power from ~150 mW (per bipolar PAL) to near-zero, a 90%+ reduction. The 20 ns tPD matches the speed of the bipolar PALs being replaced, ensuring timing compatibility. The architectural advantage is that all 16 macrocells share a unified AND/OR array, eliminating the routing delays and signal integrity issues that arise from daisy-chaining separate PALs. Designers migrating from PALs to the EP610PC-20 also gain the security bit and the ability to reprogram during prototyping.
Recommended
Recommended Products Summary
Engineering reference data for EP610PC-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610PC-15 | EP610DC-25 | EP610DC-20 | EP610DC-15 | EP610PC-20T |
|---|---|---|---|---|---|---|
| Package | PDIP-24 | PDIP-24 - same | CDIP-24 - same 24-pin DIP footprint | CDIP-24 - same 24-pin DIP footprint | CDIP-24 - same 24-pin DIP footprint | PDIP-24 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tPD) | 20 ns | 15 ns (faster) | 25 ns (slower) | 20 ns (same) | 15 ns (faster) | 20 ns (same) |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 300 | 300 | 300 | 300 | 300 | 300 |
| Supply Voltage | 5 V ±10% | 5 V ±10% | 5 V ±10% | 5 V ±10% | 5 V ±10% | 5 V ±10% |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | -55C to +125C (military) | -55C to +125C (military) | -55C to +125C (military) | 0C to +70C |
| Process Technology | CMOS EPROM | CMOS EPROM | CMOS EPROM (ceramic) | CMOS EPROM (ceramic) | CMOS EPROM (ceramic) | CMOS EPROM |
Key Differentiators
- Faster propagation delay in the same PDIP-24 footprint (vs EP610DC-25)
- Commercial-temperature plastic package at lower cost (vs EP610DC-20)
- Lower commercial price point (qty-1, 2026-09-10) (vs EP610PC-15)
Design Notes
The EP610PC-20 operates from a single 5 V ±10% supply. Place a 0.1 µF ceramic decoupling capacitor as close as possible to the VCC pin (pin 22), and add a 10 µF tantalum bulk capacitor near the device to handle switching transients. The CMOS EPROM technology gives near-zero standby current, but dynamic current during clock edges can reach 30-50 mA; adequate decoupling prevents VCC droop that would propagate as ground-bounce into the TTL output drivers. For multi-EPLD boards, use a star-ground topology to prevent switching noise from coupling into analog sections.
Critical pitfall: the -20 speed grade may violate timing margins if the original design assumed the -15 grade. Check that tCO (clock-to-output), tSU (setup time), and tH (hold time) at the actual operating frequency stay within the datasheet limits. Also verify that the device programmer (e.g., Data I/O, BP-1200) supports the Classic EPLD JEDEC fuse-map format — older programmers may not recognize the EP610 algorithm. Finally, the windowed ceramic variant requires quartz window exposure to UV (typically 20-30 min at 12 mW/cm²) before reprogramming; do not exceed the 1000-erase cycle limit specified in the datasheet.
The PDIP-24 through-hole package is robust for through-hole assembly but consumes significant board area. Keep at least 100 mils of clearance around the device for socket insertion (if used) and for inspection of solder joints. For high-speed designs with signals >50 MHz, the lead inductance of the PDIP package (~5 nH per pin) can introduce ringing; consider the EP610JC-20 PLCC variant or the EP610LC-20 JLCC variant for surface-mount designs. If using a socket, specify a low-profile machined-pin socket (e.g., Aries 24-pin) to minimize parasitic inductance at frequencies approaching the 100 MHz pipelined limit.
Compliance Information
Legacy PDIP-24 plastic package is non-RoHS due to SnPb lead finish typical of the original 1980s-1990s manufacturing era. For RoHS-compliant modern systems, source through authorized resellers that have re-qualified the part, or migrate to a MAX II CPLD equivalent.
