EP9100C-30 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP9100C-30 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP9100C-30 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $15.60 |
| Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Logic Density | 900 usable gates (approx.) | β |
| Macrocells | 48 | 24 |
| Flip-Flops | 24 | β |
| Dedicated Inputs | 24 | 36 |
| Propagation Delay (tPD) | 30 ns | 30 ns (max) |
| Maximum Toggle Frequency (fMAX) | 62.5 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | β |
| I/O Standard | TTL-compatible | β |
| Technology | CMOS, UV-erasable (window) or OTP | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Package | 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP | DIP-40 (through-hole, 600 mil) |
| Programming Method | JEDEC via Altera APU or compatible programmer | UV-Erasable / OTP |
| Mounting Type | Through-Hole (DIP) / Surface Mount (PLCC) | Through-Hole |
| RoHS Status | [DATA_NEEDED: rohs_status] | β |
| Military Grade Variant | EP9100C-30/883 (MIL-STD-883 compliant) | β |
| Architecture | β | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | β | 900 usable gates |
| Clock Frequency (fCNT) | β | 33.3 MHz |
| Outputs (Macrocells) | β | 24 |
| External Clock Pins | β | 2 (CLK1, CLK2) |
| Supply Voltage | β | 5 V |
| Process Technology | β | CMOS |