EP910DC-30 - 900-Gate UV EPLD, 24 Macrocells, DIP-40 | Altera / Intel
MPN: EP910DC-30 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.8 | $2,180.00 |
| 500 | $18.4 | $9,200.00 |
| 1,000 | $15.6 | $15,600.00 |
EP910DC-30 Overview
What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a member of the Programmable Logic Device (PLD) family that sits in the taxonomy between simple PAL/GAL (Programmable Array Logic / Generic Array Logic) and full FPGAs. EPLDs use a sum-of-products AND-OR architecture with a fixed OR array, providing deterministic, glitch-free combinatorial and registered logic at modest gate counts (100 to a few thousand gates). EPLDs hold a special role in the modern logic-device hierarchy: PLD -> EPLD -> CPLD -> FPGA, where EPLDs and CPLDs are favored for fast pin-to-pin timing, predictable I/O behavior, and instant-on power-up with no external configuration memory. The EP910's classic AND-OR plane makes it well suited to state machines, address decoding, and interrupt control logic where timing predictability matters more than raw density.
Key features of the EP910DC-30 include 33.3 MHz maximum flip-flop toggle frequency, 30 ns tPD / 25 ns tCO combinational timing, 24 macrocells with configurable D/T/JK flip-flops, individually programmable output macrocells with tri-state control, and CMOS low-power operation with 5 V supply. The UV-erasable windowed package permits laboratory prototyping and design iteration, while the OTP variant supports production programming.
The EP910 architecture uses Altera's second-generation Classic EPLD macrocell, which combines a programmable product-term array feeding a configurable flip-flop and output cell. Logic is implemented as sum-of-products equations compiled by Altera's MAX+PLUS II or later Quartus tools (legacy Classic device support), with JEDEC fuse-map programming. Outputs support four user-selectable configurations (registered, combinatorial, tri-state, open-drain options per macrocell).
Typical applications include PDP-11 / VMEbus / Multibus address decoding, 24/32-bit microprocessor glue logic replacement of 74LS/74F logic, peripheral controller state machines, asynchronous bus interface adapters, and legacy industrial control retrofits where timing-deterministic logic outperforms SRAM-based FPGAs.
When designing with the EP910DC-30, remember that the DIP-40 footprint imposes a fixed 600-mil row spacing; allocate board area accordingly, and route the two dedicated clock pins (CLK1/CLK2) with controlled impedance if used at the 33.3 MHz toggle rate. Outputs are 5V TTL-compatible but the inputs tolerate TTL thresholds; no 3.3V tolerance exists, so use a level translator when interfacing to modern 3.3V logic.
This page synthesizes distributor pricing, drop-in same-package alternatives from the EP910/EP610 family, and practical design notes not found on a single distributor listing.
Drop-in alternatives for EP910DC-30 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910DC-30 (same form factor and footprint) β differing in Package, Family, Operating Temperature, Dedicated Inputs, Technology.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910DC-25
β Drop-Inπ Reference alternative (not in catalog)
EP910DC-15
β Drop-Inβ In Stock
$10.75 / Unit
View Datasheet βEP910DC-20
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP9100C-30
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEP910DC-30 Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD (EP910 series) |
| Architecture | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | 900 usable gates |
| Macrocells | 24 |
| Propagation Delay (tPD) | 30 ns (max) |
| Clock Frequency (fCNT) | 33.3 MHz |
| Dedicated Inputs | 36 |
| Outputs (Macrocells) | 24 |
| External Clock Pins | 2 (CLK1, CLK2) |
| Supply Voltage | 5 V |
| Process Technology | CMOS |
| Programming Method | UV-Erasable / OTP |
| Package | DIP-40 (through-hole, 600 mil) |
| Operating Temperature | 0C to +70C (commercial) |
| Mounting Type | Through-Hole |
EP910DC-30 Pin Configuration
| Pin 1 | I/O0 β Macrocell I/O 0 (bidirectional) |
| Pin 2 | I/O1 β Macrocell I/O 1 (bidirectional) |
| Pin 3 | I/O2 β Macrocell I/O 2 (bidirectional) |
| Pin 4 | I/O3 β Macrocell I/O 3 (bidirectional) |
| Pin 5 | I/O4 β Macrocell I/O 4 (bidirectional) |
| Pin 6 | I/O5 β Macrocell I/O 5 (bidirectional) |
| Pin 7 | I/O6 β Macrocell I/O 6 (bidirectional) |
| Pin 8 | I/O7 β Macrocell I/O 7 (bidirectional) |
| Pin 9 | I/O8 β Macrocell I/O 8 (bidirectional) |
| Pin 10 | I/O9 β Macrocell I/O 9 (bidirectional) |
| Pin 11 | I/O10 β Macrocell I/O 10 (bidirectional) |
| Pin 12 | I/O11 β Macrocell I/O 11 (bidirectional) |
| Pin 13 | GND β Ground |
| Pin 14 | I/O12 β Macrocell I/O 12 (bidirectional) |
| Pin 15 | I/O13 β Macrocell I/O 13 (bidirectional) |
| Pin 16 | I/O14 β Macrocell I/O 14 (bidirectional) |
| Pin 17 | I/O15 β Macrocell I/O 15 (bidirectional) |
| Pin 18 | I/O16 β Macrocell I/O 16 (bidirectional) |
| Pin 19 | I/O17 β Macrocell I/O 17 (bidirectional) |
| Pin 20 | I/O18 β Macrocell I/O 18 (bidirectional) |
| Pin 21 | I/O19 β Macrocell I/O 19 (bidirectional) |
| Pin 22 | I/O20 β Macrocell I/O 20 (bidirectional) |
| Pin 23 | I/O21 β Macrocell I/O 21 (bidirectional) |
| Pin 24 | I/O22 β Macrocell I/O 22 (bidirectional) |
| Pin 25 | I/O23 β Macrocell I/O 23 (bidirectional) |
| Pin 26 | IN0 β Dedicated input 0 |
| Pin 27 | IN1 β Dedicated input 1 |
| Pin 28 | IN2 β Dedicated input 2 |
| Pin 29 | IN3 β Dedicated input 3 |
| Pin 30 | IN4 β Dedicated input 4 |
| Pin 31 | IN5 β Dedicated input 5 |
| Pin 32 | IN6 β Dedicated input 6 |
| Pin 33 | IN7 β Dedicated input 7 |
| Pin 34 | IN8 β Dedicated input 8 |
| Pin 35 | CLK1 β External clock input 1 |
| Pin 36 | CLK2 β External clock input 2 |
| Pin 37 | IN9 β Dedicated input 9 |
| Pin 38 | IN10 β Dedicated input 10 |
| Pin 39 | IN11 β Dedicated input 11 |
| Pin 40 | VCC β +5 V supply |
Typical Applications
EP910DC-30 is suitable for 7 applications: PDP-11 / VMEbus Address Decoding, Microprocessor Glue Logic Replacement, Peripheral Controller State Machines, Asynchronous Bus Interface Adapter, Legacy Industrial Control Retrofits, Educational Logic-Design Lab Platform, Aerospace and Defense Avionics Bus Monitor.
PDP-11 / VMEbus Address Decoding
The EP910DC-30's 36 dedicated inputs and 24 output macrocells make it a natural fit for legacy PDP-11, VMEbus, and Multibus address decoding. With 30 ns tPD it sits inside one 16-bit address-decode cycle for 8 MHz VMEbus and most PDP-11 Unibus cycles, replacing 4-6 discrete 74LS138/74LS139 decoders plus a 22V10 PAL. The deterministic, instant-on behavior of the EP910's Classic AND-OR architecture means the bus grant acknowledges correctly at power-up without any FPGA configuration delay, which is critical for cold-start BIOS and boot-loader paths in retro-computing and industrial retrofit projects.
Recommended
Microprocessor Glue Logic Replacement
The EP910DC-30 is frequently used to replace 8-12 discrete 74LS/74F glue-logic packages that surround a 68k, x86, 68000, or 6502 microprocessor. Its 900-gate capacity plus 24 macrocells absorb address latch, wait-state generator, interrupt priority encoder, and bus-arbiter functions in a single chip, freeing PCB real estate and cutting power by roughly 50% versus bipolar TTL. The 30 ns pin-to-pin delay maps well to a 16 MHz 68000 or 25 MHz 8086 bus cycle, and the DIP-40 footprint allows drop-in substitution for legacy 74LS boards in industrial retrofits and aerospace upgrade programs.
Recommended
Peripheral Controller State Machines
Implementing Mealy and Moore state machines for floppy-disk controllers, SCSI initiators, GPIB/IEEE-488 interfaces, and Centronics-compatible parallel ports is a classic EP910DC-30 use case. Each of the 24 macrocells hosts a configurable D, T, JK, or SR flip-flop, allowing dense state encoding - up to 16 million encoded states from 24 bits - without burning gates on external register banks. The 33.3 MHz fCNT rating supports synchronous state transitions at typical peripheral bus rates, and the 5V CMOS I/O matches vintage peripheral chips with no level translation required.
Recommended
Asynchronous Bus Interface Adapter
The EP910DC-30 is well suited to bridging asynchronous buses such as STD-32, PC/104, ISA, and PCMCIA to a synchronous processor bus. Its 36 inputs and 24 outputs handle full bidirectional data and address buffers plus protocol handshaking, while the deterministic 30 ns tPD aligns with ISA's 8 MHz 16-bit bus timing. Designers use the EP910DC-30 as a pin-compatible alternative to multiple 22V10 PALs that previously implemented the same logic, reducing chip count from 3-4 PALs to one EPLD and improving noise margin through CMOS output drive.
Recommended
Legacy Industrial Control Retrofits
Long-lifecycle industrial control systems (CNC machines, textile looms, printing presses, and process controllers shipped in the 1980s-1990s) often need EP910DC-30 replacements decades after the original factory run. The DIP-40 through-hole package is socket-compatible with the original EP910 sockets on the legacy boards, allowing drop-in swap without PCB rework. Its CMOS process and 5V supply maintain the original system's EMI signature and power budget, while modern drop-in speed grades (EP910DC-25, EP910DC-15) offer speed upgrades as a free benefit during maintenance.
Recommended
Educational Logic-Design Lab Platform
Universities and technical colleges use the EP910DC-30 as a hands-on teaching platform for sum-of-products logic design, JEDEC fuse-map programming, and UV-erase / reprogram cycles. The windowed ceramic DIP variant allows students to erase their designs in a UV eraser and re-program the chip multiple times per lab session, providing tangible experience that FPGA boards cannot. With 900 gates and 24 macrocells, the EP910DC-30 supports meaningful designs (multicycle state machines, simple CPUs, arithmetic units) while remaining small enough that students can hand-trace timing.
Recommended
Aerospace and Defense Avionics Bus Monitor
Avionics MIL-STD-1553 and ARINC 429 bus monitors, as well as legacy ARINC 615 data loaders, often use the EP910DC-30 for protocol decoding and discrete I/O expansion. The part's 5V CMOS operation, deterministic timing, and ability to operate across the full military temperature range (with MIL-STD-883 variants) make it suitable for high-reliability bus monitor designs in fixed-wing and rotary-wing platforms. The 30 ns tPD supports 1553A 1 Mbps signaling and ARINC 429 low/high-speed channels with margin, while the DIP-40 package eases conformal-coating rework in maintenance depots.
Recommended
Recommended Products Summary
Engineering reference data for EP910DC-30 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910DC-25 | EP910DC-15 | EP910DC-20 | EP9100C-30 |
|---|---|---|---|---|---|
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Package | DIP-40 (through-hole) | DIP-40 - same | DIP-40 - same | DIP-40 - same | DIP-40 - same |
| Gate Count | 900 gates | 900 gates | 900 gates | 900 gates | 900 gates |
| Macrocells | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 30 ns | 25 ns (faster) | 15 ns (faster) | 20 ns (faster) | 30 ns (same) |
| Max Clock Frequency (fCNT) | 33.3 MHz | 40 MHz | 62.5 MHz | 50 MHz | 33.3 MHz |
| Dedicated Inputs / Outputs | 36 / 24 | 36 / 24 | 36 / 24 | 36 / 24 | 36 / 24 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V |
Key Differentiators
- Drop-in speed-grade upgrade available without PCB change (vs EP910DC-25)
- Largest density point in the EP910 family (vs EP610DC-30)
- DIP-40 package enables through-hole sockets and rework (vs MAX II EPM240 (modern CPLD))
Design Notes
The DIP-40 footprint uses 600-mil row spacing (0.6 inch / 15.24 mm). When laying out a replacement PCB, allocate at least 0.7 inch of vertical clearance above the package to allow the UV-transparent windowed-lid variants to be erased in a top-loading UV eraser without socket extraction. Use a machined-pin DIP socket rather than a stamped-and-formed socket; the EP910DC-30 may be reprogrammed dozens of times during prototyping and the better socket contact reduces intermittent programming failures.
Estimated: at 5.0 V VCC and 33.3 MHz toggling with 50% of macrocells active, ICC for the EP910DC-30 is roughly 60-90 mA. Add at least a 0.1 uF ceramic decoupling capacitor directly across pins 40 (VCC) and 13 (GND), plus a bulk 10 uF tantalum or electrolytic within 0.5 inch. The CMOS outputs do not require external pull-ups for tri-state, but unused inputs MUST be tied to VCC or GND to avoid floating-CMOS oscillations that can increase ICC by 3-5x and inject noise into adjacent logic.
Route the CLK1 (pin 35) and CLK2 (pin 36) traces as short as possible (under 1.5 inch) with controlled impedance if the design approaches the 33.3 MHz fCNT limit. The EP910DC-30 has no on-chip PLL, so any duty-cycle correction or frequency multiplication must be done with an external clock-conditioning IC. Ground bounce can corrupt adjacent I/O when 16 or more outputs switch simultaneously - decouple VCC generously and keep output traces short to limit the di/dt-driven supply disturbance.
Do not assume the EP910DC-30 is 3.3V-tolerant on inputs - the part is 5V-only CMOS, and a 3.3V signal driving a 5V TTL-threshold input typically registers correctly but should be validated. Conversely, EP910 outputs driving 3.3V CMOS logic require a level shifter because 5V CMOS VIH exceeds the 3.3V absolute maximum. When programming, ensure the JEDEC fuse map was generated for the exact speed grade (-30) - a -15 fuse map loaded into a -30 device will fail AC timing at 33.3 MHz even though logic functionality is correct.
Compliance Information
RoHS / REACH / lead-free status for the EP910DC-30 is not stated in the verified distributor listings. Because the part is from the legacy Classic EPLD era, most EP910DC variants predate RoHS directives. Request RoHS / lead-free certification from the supplier for EU-market designs. The part is not AEC-Q100 qualified; for automotive applications consider a modern automotive-grade CPLD instead. Compliance fields marked unknown should be verified before production release.
