EP9100C-30 vs EP910DI-30 Comparison

Detailed side-by-side comparison of EP9100C-30 by Altera and EP910DI-30 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP9100C-30 EP910DI-30
Brand Altera Rochester Electronics
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $7.95 $17.60
Family Altera Classic EPLD Classic EPLD (Altera EP910 series)
Logic Density 900 usable gates (approx.) β€”
Macrocells 48 β€”
Flip-Flops 24 β€”
Dedicated Inputs 24 10
Propagation Delay (tPD) 30 ns β€”
Maximum Toggle Frequency (fMAX) 62.5 MHz β€”
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (single supply)
I/O Standard TTL-compatible β€”
Technology CMOS, UV-erasable (window) or OTP CMOS, UV-erasable EPROM
Operating Temperature 0C to +70C (commercial) -40C to +85C (industrial)
Package 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP CDIP-40 (ceramic DIP, 40-pin with UV window)
Programming Method JEDEC via Altera APU or compatible programmer β€”
Mounting Type Through-Hole (DIP) / Surface Mount (PLCC) Through-Hole (DIP)
RoHS Status [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS compliance status]
Military Grade Variant EP9100C-30/883 (MIL-STD-883 compliant) β€”
Product Type β€” UV-Erasable Programmable Logic Device (EPLD)
Macrocell Count β€” 24
Propagation Delay (tpd) β€” 30 ns
Maximum Toggle Frequency (fmax) β€” 62 MHz
Dedicated I/O Pins β€” 12 (12 input + 12 output)
Output Enable Pins β€” 2
Pin Count β€” 40
Programmable Logic Element β€” JEDEC fuse map (3rd-party programmer)
Manufacturer (Original) β€” Altera (now Intel PSG)
Current Distributor / Authorized Aftermarket β€” Rochester Electronics, LLC

Datasheets & Resources

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