EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
MPN: EP910DI-30 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.3 | $253.00 |
| 100 | $22.1 | $2,210.00 |
| 250 | $19.85 | $4,962.50 |
| 500 | $17.6 | $8,800.00 |
EP910DI-30 Overview
A programmable logic device (PLD) is a general-purpose digital IC whose logic function is set by the end user via on-chip fuses, anti-fuses, EPROM, EEPROM, or SRAM configuration cells. EPLDs sit in the product-type hierarchy: programmable logic device -> erasable PLD -> complex PLD (CPLD) -> semiconductor -> integrated circuit. They were historically used as glue logic, address decoding, state machines, and bus-interface bridges before modern FPGAs and CPLDs took over most of those roles.
Key features of the EP910DI-30 include 24 macrocells, 50% of which are user-configurable as registered or combinatorial outputs, 10 dedicated input pins, 12 dedicated I/O pins, and a maximum toggle frequency of 62 MHz. The device operates from a single 5 V supply and is windowed (UV-erasable) for design iteration - it must be removed from the circuit and exposed to UV light to erase. The 30 ns speed grade suits asynchronous state machines, address decoders, and bus-interface logic in legacy 5 V systems.
The 40-pin ceramic DIP package is a through-hole form factor with a quartz window on top for erasure, and provides robust thermal and mechanical performance suitable for industrial and military temperature grades. Because the part is supplied through Rochester Electronics (the authorized aftermarket manufacturer for legacy Altera EPLDs), it is targeted at long-lifecycle programs that must keep a 20-30 year production run alive.
Typical applications include legacy bus-interface bridging (e.g., 8-bit to 16-bit address demultiplexing), glue logic in industrial controllers, replacement of discrete TTL/MSI logic in avionics and military systems, and state-machine controllers in medical and test equipment where redesign is impractical. Because of the CDIP-40 footprint and 5 V supply, the EP910DI-30 drops directly into boards originally designed for the EP910 family.
When designing with this device, engineers should note that modern design tools no longer natively support the EP910 family - programming is typically done with legacy Altera hardware or third-party JEDEC-file programmers. The 5 V supply rail should be well decoupled with 0.1 uF ceramic capacitors adjacent to each VCC/GND pair, and unused inputs must be tied to VCC or GND through a defined logic level rather than left floating.
This page synthesizes Rochester Electronics distributor stock data, JEDEC-file programming considerations, and drop-in alternatives for the Classic EPLD family - practical engineering context not found in the original manufacturer datasheet alone.
Drop-in alternatives for EP910DI-30 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910DI-30 (same form factor and footprint) — differing in Package, Family, Operating Temperature, Technology, Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910DC-30
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$15.6 / Unit
View Datasheet →EP910DC-35
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.95 / Unit
View Datasheet →EP910DC-40
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$13.95 / Unit
View Datasheet →EP910DC-15
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.75 / Unit
View Datasheet →EP9100C-30
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.95 / Unit
View Datasheet →EP910DI-30 Maximum Ratings & Electrical Characteristics
| Product Type | UV-Erasable Programmable Logic Device (EPLD) |
| Family | Classic EPLD (Altera EP910 series) |
| Macrocell Count | 24 |
| Propagation Delay (tpd) | 30 ns |
| Maximum Toggle Frequency (fmax) | 62 MHz |
| Supply Voltage (VCC) | 5 V (single supply) |
| Technology | CMOS, UV-erasable EPROM |
| Package | CDIP-40 (ceramic DIP, 40-pin with UV window) |
| Mounting Type | Through-Hole (DIP) |
| Dedicated Inputs | 10 |
| Dedicated I/O Pins | 12 (12 input + 12 output) |
| Output Enable Pins | 2 |
| Pin Count | 40 |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) |
| Operating Temperature | -40C to +85C (industrial) |
| Manufacturer (Original) | Altera (now Intel PSG) |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC |
EP910DI-30 Pin Configuration
| Pin 1 | I/O — Input/Output pin (macrocell-driven) |
| Pin 2 | I/O — Input/Output pin (macrocell-driven) |
| Pin 3 | I/O — Input/Output pin (macrocell-driven) |
| Pin 4 | I/O — Input/Output pin (macrocell-driven) |
| Pin 5 | I/O — Input/Output pin (macrocell-driven) |
| Pin 6 | I/O — Input/Output pin (macrocell-driven) |
| Pin 7 | I/O — Input/Output pin (macrocell-driven) |
| Pin 8 | I/O — Input/Output pin (macrocell-driven) |
| Pin 9 | I/O — Input/Output pin (macrocell-driven) |
| Pin 10 | I/O — Input/Output pin (macrocell-driven) |
| Pin 11 | I/O — Input/Output pin (macrocell-driven) |
| Pin 12 | I/O — Input/Output pin (macrocell-driven) |
| Pin 13 | GND — Ground |
| Pin 14 | OE — Output Enable (active low) - macrocell 1 |
| Pin 15 | INPUT — Dedicated input pin |
| Pin 16 | INPUT — Dedicated input pin |
| Pin 17 | INPUT — Dedicated input pin |
| Pin 18 | INPUT — Dedicated input pin |
| Pin 19 | INPUT — Dedicated input pin |
| Pin 20 | INPUT — Dedicated input pin |
| Pin 21 | INPUT — Dedicated input pin |
| Pin 22 | INPUT — Dedicated input pin |
| Pin 23 | INPUT — Dedicated input pin |
| Pin 24 | INPUT — Dedicated input pin (clock input) |
| Pin 25 | INPUT — Dedicated input pin |
| Pin 26 | INPUT — Dedicated input pin |
| Pin 27 | INPUT — Dedicated input pin |
| Pin 28 | INPUT — Dedicated input pin |
| Pin 29 | INPUT — Dedicated input pin |
| Pin 30 | INPUT — Dedicated input pin |
| Pin 31 | INPUT — Dedicated input pin |
| Pin 32 | INPUT — Dedicated input pin |
| Pin 33 | INPUT — Dedicated input pin |
| Pin 34 | INPUT — Dedicated input pin |
| Pin 35 | OE — Output Enable (active low) - macrocell 2 |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | VCC — +5V supply |
| Pin 39 | VCC — +5V supply |
| Pin 40 | VCC — +5V supply |
Typical Applications
EP910DI-30 is suitable for 6 applications: Legacy Bus Interface and Address Decoding, Industrial Glue Logic Replacement, Avionics and Military Long-Lifecycle Systems, State-Machine and Sequencer Controllers, Test and Measurement Instrumentation, Education and Prototyping Platforms.
Legacy Bus Interface and Address Decoding
The EP910DI-30 is widely used as a bus-interface bridge and address decoder in legacy 5V microcontroller and microprocessor systems, particularly where 8-bit to 16-bit address demultiplexing or memory-mapped peripheral chip-select generation is required. Its 24 macrocells easily implement a full 16-bit address decoder with chip-select outputs, while the 30ns tpd sits comfortably between an 8 MHz 8086 bus cycle (125ns) and a 25 MHz 80186 cycle (40ns), leaving timing margin for wait-state insertion. Placed between the CPU address bus and peripheral CS pins, the EP910DI-30 replaces several discrete 74LS138/139/688 decoder ICs with one programmable device, reducing board area and BOM cost. The 5V single-supply operation matches TTL logic rails directly, so no level shifting is required. Engineers must ensure unused inputs are tied HIGH or LOW (never floating) to avoid extra CMOS quiescent current, and that the 5V rail is decoupled with 0.1 uF ceramic capacitors adjacent to the VCC/GND pairs.
Recommended
Industrial Glue Logic Replacement
The EP910DI-30 serves as a pin-compatible replacement for aging 74LS/74ALS/MSI discrete logic in industrial controllers, PLCs, and machine-tool control boards. With 24 macrocells it can replace 4 to 6 standard decoder, multiplexer, and latch ICs in a single ceramic DIP package, simplifying long-lifecycle service and spare-parts inventories. The 30ns tpd handles typical PLC scan times in the 1-10 ms range with substantial margin, and the industrial -40C to +85C operating temperature supports factory-floor deployment. The CDIP-40 through-hole package is mechanically robust against vibration and conformal coating, which is critical in industrial environments. When substituting for a basket of 74LS ICs, designers should verify the JEDEC fuse map from the original Altera design and reuse the existing programmer output to avoid revalidation cycles.
Recommended
Avionics and Military Long-Lifecycle Systems
The EP910DI-30 remains in production through Rochester Electronics specifically for avionics, military, and aerospace programs that must keep a 20-30 year production run alive without PCB redesign. The CDIP-40 ceramic package meets MIL-STD-883 thermal and mechanical screening requirements, and the -40C to +85C industrial temperature range extends to military-aerospace temperature profiles with appropriate uprating. With 24 macrocells the EP910DI-30 implements radar interface glue logic, navigation display address decoding, and ARINC-429 bus-side state machines. The 5V supply rail aligns with legacy avionic power buses, and the 30ns tpd suits asynchronous 5V interface logic. Engineers in these markets should consult Rochester for MIL-STD-883 screening options, Group A/B/C test reports, and source-control drawings before procurement.
Recommended
State-Machine and Sequencer Controllers
The EP910DI-30 is well suited to implementing synchronous state machines, sequencers, and waveform generators in test equipment and medical instrumentation. Its 12 registered macrocell outputs can produce up to 12-bit parallel control sequences with deterministic 30ns clock-to-output delay, enabling precise timing of valve drivers, relay sequences, or A/D converter trigger pulses. The 62 MHz fmax supports state-machine clock rates up to 16 MHz when using one-hot encoding, leaving margin for safety and timing-closure verification. Housed in a CDIP-40 package, the device is mechanically robust against drop-shock and vibration in portable medical and test devices. Designers writing state machines for the EP910 should use legacy Altera AHDL or schematic capture plus the MAX+PLUS II toolchain, then export the JEDEC file for production programming.
Recommended
Test and Measurement Instrumentation
The EP910DI-30 is found inside legacy bench instruments - oscilloscopes, logic analyzers, frequency counters, and GPIB-controlled test gear - as a custom interface or front-panel logic controller. The 24-macrocell capacity supports moderate-complexity front-panel state machines and BCD-to-7-segment decoding, while the 30ns tpd is more than adequate for human-perceptible front-panel timing (millisecond update rates). The ceramic CDIP-40 package provides reliable operation over decades of bench service. Where the instrument was originally manufactured before 2000, replacing a failed EP910DI-30 with an EP910DC-30 or EP9100C-30 (same die) avoids a redesign cycle and preserves the original GPIB/SCPI command set. Engineers performing such repairs should verify that the original JEDEC fuse map is archived in the manufacturer's service documentation.
Recommended
Education and Prototyping Platforms
The EP910DI-30 is also used in university digital-logic laboratories and engineering-prototyping platforms where students learn programmable-logic fundamentals using Altera's MAX+PLUS II toolchain. The 24-macrocell complexity is appropriate for introductory combinational and sequential design exercises - decoders, counters, multiplexers, adders, and small state machines - without overwhelming a student. The 40-pin DIP form factor plugs directly into a standard breadboard or IC socket, simplifying lab wiring. Educational deployments often use the 30ns speed grade because it gives the largest timing margin for slow-clock experiments. While modern curricula have largely migrated to FPGA dev boards (e.g., Intel MAX 10, Xilinx Artix-7), the EP910DI-30 still appears in legacy labs and in industrial-training programs teaching repair of older equipment.
Recommended
Recommended Products Summary
Engineering reference data for EP910DI-30 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910DC-30 | EP910DC-35 | EP910DC-40 | EP910DC-15 | EP9100C-30 |
|---|---|---|---|---|---|---|
| Package | CDIP-40 (ceramic DIP, UV window) | CDIP-40 - same | CDIP-40 - same | CDIP-40 - same | CDIP-40 - same | CDIP-40 - same |
| Brand | Rochester Electronics (original Altera) | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tpd) | 30 ns | 30 ns | 35 ns | 40 ns | 15 ns | 30 ns |
| Macrocell Count | 24 | 24 | 24 | 24 | 24 | 24 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| Package Material | Ceramic DIP (CDIP) | Ceramic DIP (CDIP) | Ceramic DIP (CDIP) | Ceramic DIP (CDIP) | Ceramic DIP (CDIP) | Ceramic DIP (CDIP) |
Key Differentiators
- Authorized aftermarket source for legacy Altera EP910 family (vs EP910PC-30 (Rochester, plastic DIP))
- 30ns speed grade - mid-range position in EP910 family (vs EP910DC-15 (15ns speed grade))
- Industrial temperature range (vs EP910DC-30 (commercial temperature))
Design Notes
The EP910DI-30 operates from a single 5 V supply (VCC on pins 38, 39, 40). Decouple each VCC pin to its nearest GND (pin 13) with a 0.1 uF ceramic capacitor placed as close to the package body as possible. Add a bulk 10 uF tantalum or electrolytic capacitor on the 5 V rail near the device. Estimated quiescent current is approximately 100-200 mA at 5 V with all I/Os switching, so verify the 5 V regulator can source the required current with adequate thermal margin.
Unused EP910DI-30 inputs MUST be tied HIGH or LOW through a defined logic level - never left floating. Floating CMOS inputs draw additional quiescent current, can oscillate, and may cause spurious macrocell outputs. Tie unused inputs directly to VCC or GND at the package pin, not via a long trace, to avoid capacitive coupling. Additionally, ensure the 5 V supply ramp time is monotonic and within the datasheet specification to guarantee proper power-on initialization of the EPROM configuration cells.
Place the EP910DI-30 in a 40-pin IC socket (machined-pin or dual-wipe) so the UV window can be exposed for erasure without desoldering. Maintain a clear keepout above the package window of at least 5 mm for the UV eraser lamp access. For through-hole DIP layouts, use 0.1 inch (2.54 mm) pad pitch with 0.6 mm drill, and route signal traces on a 0.2 inch grid to simplify layout. The ceramic package is heavier than plastic DIP - consider mechanical support in high-vibration environments.
Although the 30 ns tpd is slow by modern standards, treat EP910DI-30 outputs as CMOS with limited drive strength (typically 4 mA IOL/IOH). Use 74LS245 or 74HC245 buffers for high-fanout buses. Avoid routing macrocell outputs adjacent to high-frequency clocks (above 25 MHz) to prevent crosstalk. The two global Output Enable pins (OE) control groups of I/Os - route these to the bus-enable signal of the target bus, not to asynchronous control logic, to prevent bus contention during transitions.
Compliance Information
EP910DI-30 is supplied through Rochester Electronics (authorized Altera aftermarket). RoHS/REACH/lead-free status is marked unknown because the original Altera Classic EPLD family pre-dates RoHS (2006) and was originally specified for 5V through-hole industrial/military markets. For MIL-STD-883 screening options contact Rochester directly. AEC-Q100 is not applicable (this is a programmable logic device, not an automotive-grade analog IC).
