EP910DC-15 vs EP910IDI-15 Comparison

Detailed side-by-side comparison of EP910DC-15 by Altera and EP910IDI-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910DC-15 EP910IDI-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $10.75 $29.00
Family Altera Classic EPLD Classic EPLD
Device Density 900 usable gates β€”
Macrocells 24 24
Logic Elements [DATA_NEEDED: exact LE count] β€”
Dedicated Inputs 12 β€”
Bidirectional I/O Pins 12 β€”
Flip-Flops 10 β€”
Product Terms per Macrocells 24 β€”
Maximum Propagation Delay (tPD) 15 ns β€”
Speed Grade 15 β€”
Supply Voltage (VCC) 5 V (typical) β€”
Operating Temperature 0C to +70C (commercial) -40C to +85C (industrial, "I" grade)
Technology CMOS EPROM, UV-erasable CMOS EPROM
Package 24-pin ceramic DIP (DC) 40-pin CDIP (CerDIP) with quartz window
Mounting Type Through-Hole Through-hole (DIP)
MSL Level [DATA_NEEDED: MSL level] β€”
RoHS Status [DATA_NEEDED: not explicitly stated in verified data] [DATA_NEEDED: RoHS compliance of CDIP windowed part]
Device Type β€” CPLD (Complex Programmable Logic Device)
Logic Gates β€” 450 gates
Maximum User I/O Pins β€” 36
Pin-to-Pin Propagation Delay (tpd) β€” 15 ns
Maximum Counter Frequency β€” 66.6 MHz
Supply Voltage (Vcc) β€” 5 V
Program/Erase Method β€” UV-erasable windowed CerDIP
Macrocells Configurable As β€” D, T, JK, SR flip-flop, or combinatorial
Development Tool β€” MAX+PLUS II (legacy) / Altera Classic compiler
Programming Hardware β€” Altera Logic Programmer card
Logic Family Compatibility β€” Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages

Datasheets & Resources

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