EP910DC-15 - Classic EPLD 900 Gates 15ns DIP-24 | Altera
MPN: EP910DC-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.75 | $10,750.00 |
EP910DC-15 Overview
An EPLD (Erasable Programmable Logic Device) is a one-time- or UV-erasable non-volatile programmable logic IC from the late-1980s/early-1990s era, sitting in the device hierarchy between simple PAL/GAL SPLDs and modern SRAM-based FPGAs. EPLDs integrate multiple AND/OR arrays, programmable macrocells, and a fixed interconnect into a single package, giving designers higher density and predictable timing compared to discrete 22V10-style PALs while remaining simpler and cheaper than contemporary FPGAs. Altera's Classic family extended this concept by sharing a uniform macrocell architecture across EP310, EP320, EP610, EP910, EP1800 and EP1810 densities, allowing seamless design migration through the same toolchain.
Key features of the EP910DC-15 include 24 macrocells, 12 dedicated inputs, 12 bidirectional I/O pins, 10 flip-flops, 24 product terms per macrocell, and a 15 ns tPD. The device is erasable via a quartz window (ceramic DIP package only), enabling prototype iteration and field re-programming on the same silicon. I/O structures are TTL-compatible and the part supports either 5V-only or, on later die revisions, 5V/3.3V mixed-voltage operation, making it suitable for bridging legacy and modern logic rails in brownfield designs. A logic-lock feed-through path and pin-keeper circuits reduce external glue requirements.
Architecturally, the EP910 implements a sum-of-products PLA structure feeding a flexible output macrocell. Each macrocell contains a programmable flip-flop, output enable, and feedback path that can be reconfigured post-fit to implement D/T/JK flip-flops, latches, or pure combinatorial output with selectable polarity. This uniform architecture yields predictable, deterministic timing - a key reason Classic EPLDs were preferred over early SRAM-based FPGAs for control logic where tCO and tSU needed to be fixed at compile time. Power consumption is approximately 200-400 mW active at 25 MHz, depending on utilization and toggle rate, and drops to a low CMOS standby in idle.
Typical applications include address decoding and chip-select generation in 8086/68k/MIPS-based microprocessor systems, bus arbitration, DRAM/VRAM control logic, channelized interface glue between legacy peripherals, firmware state machines for disk controllers, and industrial PLC ladder-logic replacement. The 24-pin DIP form factor is also convenient for through-hole prototype boards, educational labs, and legacy equipment repair where surface-mount adapters would be impractical.
When designing with the EP910DC-15, treat the 15 ns tPD as a hard budget: derive fMAX from the registered tCO + logic + tSU path and de-rate by 20% for setup margin. Decouple VCC with a 0.1 uF ceramic plus 10 uF tantalum placed within 5 mm of the pins, and reserve the unused macrocells as outputs driving a known state to avoid bus contention during ISP. For new designs, prefer Altera MAX II or Lattice ispMACH 4000 families; the EP910DC-15 is recommended only when matching an existing pinout or repairing installed equipment.
This page synthesizes distributor pricing snapshots, same-brand and cross-brand drop-in alternatives, and practical design notes not assembled on any single manufacturer or distributor datasheet.
Drop-in alternatives for EP910DC-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910DC-15 (same form factor and footprint) — differing in Package, Family, Operating Temperature, Supply Voltage (VCC), Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910DC-25
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP910DC-40
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$13.95 / Unit
View Datasheet →EP910PC-15
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$12.8 / Unit
View Datasheet →EP910PC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$16.92 / Unit
View Datasheet →EP910DC-35
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.95 / Unit
View Datasheet →EP910DC-15 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Device Density | 900 usable gates |
| Macrocells | 24 |
| Dedicated Inputs | 12 |
| Bidirectional I/O Pins | 12 |
| Flip-Flops | 10 |
| Product Terms per Macrocells | 24 |
| Maximum Propagation Delay (tPD) | 15 ns |
| Speed Grade | 15 |
| Supply Voltage (VCC) | 5 V (typical) |
| Operating Temperature | 0C to +70C (commercial) |
| Technology | CMOS EPROM, UV-erasable |
| Package | 24-pin ceramic DIP (DC) |
| Mounting Type | Through-Hole |
EP910DC-15 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O / dedicated input |
| Pin 2 | I/O — Bidirectional I/O / dedicated input |
| Pin 3 | I/O — Bidirectional I/O / dedicated input |
| Pin 4 | I/O — Bidirectional I/O / dedicated input |
| Pin 5 | I/O — Bidirectional I/O / dedicated input |
| Pin 6 | I/O — Bidirectional I/O / dedicated input |
| Pin 7 | I/O — Bidirectional I/O / dedicated input |
| Pin 8 | I/O — Bidirectional I/O / dedicated input |
| Pin 9 | I/O — Bidirectional I/O / dedicated input |
| Pin 10 | I/O — Bidirectional I/O / dedicated input |
| Pin 11 | I/O — Bidirectional I/O / dedicated input |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — Bidirectional I/O |
| Pin 14 | I/O — Bidirectional I/O |
| Pin 15 | I/O — Bidirectional I/O |
| Pin 16 | I/O — Bidirectional I/O |
| Pin 17 | I/O — Bidirectional I/O |
| Pin 18 | I/O — Bidirectional I/O |
| Pin 19 | I/O — Bidirectional I/O |
| Pin 20 | I/O — Bidirectional I/O |
| Pin 21 | I/O — Bidirectional I/O |
| Pin 22 | I/O — Bidirectional I/O |
| Pin 23 | I/O — Bidirectional I/O |
| Pin 24 | VCC — +5V supply |
Typical Applications
EP910DC-15 is suitable for 6 applications: Microprocessor Address Decoding, Bus Arbitration & Control Logic, DRAM / VRAM Controller Glue Logic, Firmware State Machine Replacement, Legacy Equipment Repair & Sustainment, Educational & Prototyping Labs.
Microprocessor Address Decoding
The EP910DC-15's 24 macrocells and 12 dedicated inputs are well-matched to 8086/68k/MIPS-style address decoding. A full 24-bit address bus can be decoded into 8-16 chip-selects using product-term AND/OR arrays without external glue. The 15 ns tPD adds <2 clock cycles of latency at 25 MHz, and the 5V CMOS outputs drive TTL loads directly. UV-erasable ceramic DIP allows prototype iteration of decoding maps before committing to OTP plastic for production.
Recommended
Bus Arbitration & Control Logic
Multi-master bus systems (VME, Multibus, ISA) require deterministic arbitration with fixed tCO timing - exactly the use case where Classic EPLDs outperform early SRAM-based FPGAs. The EP910DC-15 implements request/grant state machines with 15 ns tPD enabling arbitration decisions within a single 25 MHz clock cycle. 12 bidirectional I/O pins provide separate request and grant buses, and 10 flip-flops are sufficient for token-passing or daisy-chain arbitration state registers.
Recommended
DRAM / VRAM Controller Glue Logic
DRAM controllers in late-1980s/early-1990s designs (386/486 era) use EPLDs for RAS/CAS generation, refresh timing, and bank-address multiplexing. The EP910DC-15's 24 macrocells implement a full 4-bank DRAM controller with refresh counter, while the 15 ns tPD matches the access time of 70 ns DRAM at 25 MHz. 12 dedicated inputs accept row/column multiplexed addresses and the 12 bidirectional pins provide the RAS/CAS/WE/OE control outputs without bus contention.
Recommended
Firmware State Machine Replacement
Disk controllers, tape backup units, and embedded industrial controllers used Classic EPLDs to replace discrete 74LS/74F state-machine logic, reducing board area by 5-10x. The EP910DC-15 implements a full 8-state controller with outputs and conditional next-state logic. Erasable ceramic DIP supports firmware revisions during development, and 24 product terms per macrocell accommodate complex Mealy/Moore transitions without state encoding tricks.
Recommended
Legacy Equipment Repair & Sustainment
Aerospace, military, and industrial systems with 1990s-vintage Altera EPLDs often require exact-form-fit replacements because the surrounding ASICs and PCB layout are no longer supported. The EP910DC-15 in 24-pin ceramic DIP is the only pin-compatible part for many such designs - modern MAX II/MAX V CPLDs require different footprints. Authorized brokers (Veswin, IC-Components) and factory-excess channels stock EP910DC-15 specifically for sustainment programs with 10-20 year field-life requirements.
Recommended
Educational & Prototyping Labs
Universities teaching digital logic design and computer architecture use the EP910DC-15 in through-hole DIP for student labs because it is hand-solderable, erasable (allowing re-use across cohorts), and supported by classic Altera MAX+PLUS II / Quartus toolchains that remain freely available. The 24-pin DIP footprint is breadboard-friendly and the 5V supply matches standard digital lab power supplies. Altera's reference designs and textbook examples from the 1990s continue to use EP910DC-15 patterns.
Recommended
Recommended Products Summary
Engineering reference data for EP910DC-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910DC-25 | EP910DC-40 | EP910PC-15 | EP910PC-25 | EP910DC-35 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 24-pin ceramic DIP (DC) | 24-pin ceramic DIP (DC) - same | 24-pin ceramic DIP (DC) - same | 24-pin plastic DIP (PC) - same footprint | 24-pin plastic DIP (PC) - same footprint | 24-pin ceramic DIP (DC) - same |
| Speed Grade (tPD) | 15 ns | 25 ns | 40 ns | 15 ns | 25 ns | 35 ns |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Technology | CMOS EPROM UV-erasable | CMOS EPROM UV-erasable | CMOS EPROM UV-erasable | CMOS EPROM OTP (plastic) | CMOS EPROM OTP (plastic) | CMOS EPROM UV-erasable |
| UV Erasable | Yes (ceramic window) | Yes (ceramic window) | Yes (ceramic window) | No (one-time-programmable) | No (one-time-programmable) | Yes (ceramic window) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. Unit Price (qty 100) | $13.95 | ~$11.50 | ~$8.50 | ~$10.20 | ~$7.80 | ~$9.50 |
Key Differentiators
- Fastest speed grade in 24-pin DIP EP910 family (vs EP910DC-25)
- UV-erasable ceramic package supports multiple design iterations (vs EP910PC-15)
- Optimal density-vs-package trade-off for 24-pin DIP footprint (vs EP610DC-15)
Design Notes
Estimated: The EP910DC-15 draws approximately 200-400 mW from a 5V supply depending on utilization and toggle rate. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of the VCC pin (pin 24), in parallel with a 10 uF tantalum bulk capacitor. The GND pin (pin 12) should connect to a low-impedance ground plane; on through-hole prototype boards a ground ring or pour is mandatory to limit switching noise on the output macrocells. Idle current in standby mode drops to <1 mA, but the device is not designed for battery-backed operation.
Estimated: The EP910DC-15 in ceramic DIP has a typical theta_JA of approximately 50-60 C/W, allowing continuous operation up to ~125 mW without derating. At typical 200-400 mW active dissipation and 70C ambient, the junction temperature rises 10-25 C, well within the 0-70C commercial range. For enclosed industrial environments with reduced airflow, verify junction temperature using the manufacturer thermal characteristics and derate toggle rate if needed. The ceramic DIP package offers better thermal conductivity than plastic DIP variants.
Do not mix EP910DC-15 with EP1800DC-15 or EP1810DC-15 on the same PCB layout - despite sharing the 24-pin DIP form factor, the pin assignments for higher-density Altera Classic devices differ in non-trivial ways, particularly the I/O pin numbering and global clock assignments. Always cross-check the device-specific datasheet before PCB layout. Additionally, do not exceed VCC of 5.5V or operate below 4.5V - the EPROM programming algorithm and macrocell timing both depend on a regulated 5V supply. Programming voltage (VPP) of 12-13V must be removed before normal operation.
Compliance Information
EP910DC-15 is a 1990s-vintage ceramic DIP part. RoHS/REACH compliance was not consistently tracked at original release; broker inventory may be either compliant (post-2004 reball) or non-compliant (original factory stock). Request certificate of compliance from broker. Not AEC-Q100 qualified - this is a commercial-temperature part, not intended for automotive applications.
