EP910DC-30 vs EP610DC-30 Comparison
Detailed side-by-side comparison of EP910DC-30 by Intel and EP610DC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-30 | EP610DC-30 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.60 | $10.40 |
| Family | Classic EPLD (EP910 series) | EP610 (Classic Device Family) |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | β |
| Gate Count | 900 usable gates | β |
| Macrocells | 24 | 16 |
| Propagation Delay (tPD) | 30 ns (max) | 30 ns |
| Clock Frequency (fCNT) | 33.3 MHz | β |
| Dedicated Inputs | 36 | 16 |
| Outputs (Macrocells) | 24 | β |
| External Clock Pins | 2 (CLK1, CLK2) | β |
| Supply Voltage | 5 V | β |
| Process Technology | CMOS | β |
| Programming Method | UV-Erasable / OTP | β |
| Package | DIP-40 (through-hole, 600 mil) | 24-pin CERDIP (windowed) |
| Operating Temperature | 0C to +70C (commercial) | Commercial (0C to +70C) |
| Mounting Type | Through-Hole | Through-Hole |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Expanders | β | 4 (4 product terms per macrocell) |
| Usable Gates | β | 300 |
| Maximum Pipelined Clock Frequency | β | 100 MHz |
| I/O Pins | β | 16 (with output enable) |
| Speed Grade | β | -30 (30 ns tPD) |
| Technology | β | CMOS EPROM |
| Programmability | β | UV-erasable, windowed EPROM |
| Security Bit | β | Yes (protects design after programming) |
| Output Modes | β | Registered and Combinatorial |