EP910DC-30 vs EP910DC-40 Comparison
Detailed side-by-side comparison of EP910DC-30 by Intel and EP910DC-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP910DC-30
EP910DC-30 - 900-Gate UV EPLD, 24 Macrocells, DIP-40 | Altera / Intel
EP910DC-30 ObsoleteSpecification Comparison
| Parameter | EP910DC-30 | EP910DC-40 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.60 | $13.95 |
| Family | Classic EPLD (EP910 series) | β |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | PAL-type AND/OR, UV-erasable CMOS |
| Gate Count | 900 usable gates | β |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | β |
| Clock Frequency (fCNT) | 33.3 MHz | β |
| Dedicated Inputs | 36 | 12 |
| Outputs (Macrocells) | 24 | β |
| External Clock Pins | 2 (CLK1, CLK2) | β |
| Supply Voltage | 5 V | 5 V (typical for Classic EPLD family) |
| Process Technology | CMOS | β |
| Programming Method | UV-Erasable / OTP | UV-erase + EPROM programmer; on-board logic test circuitry |
| Package | DIP-40 (through-hole, 600 mil) | DIP-40 (ceramic, through-hole) |
| Operating Temperature | 0C to +70C (commercial) | β |
| Mounting Type | Through-Hole | Through-Hole |
| Device Family | β | Classic EPLD (EP910 series) |
| Bidirectional I/O Pins | β | 24 |
| Total Inputs to Logic Array | β | 36 |
| Product Terms | β | 240 maximum |
| Maximum Propagation Delay (tPD) | β | 40 ns |
| Maximum Operating Frequency (fMAX) | β | 25 MHz |
| Global Clocks | β | 2 |
| Operating Temperature (Commercial) | β | 0 Β°C to 70 Β°C |
| RoHS Status | β | [DATA_NEEDED: rohs_status] |