EP910DC-40 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910DC-40 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP910DC-30
EP910DC-30 - 900-Gate UV EPLD, 24 Macrocells, DIP-40 | Altera / Intel
EP910DC-30 ObsoleteSpecification Comparison
| Parameter | EP910DC-40 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.95 | $15.60 |
| Device Family | Classic EPLD (EP910 series) | β |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | PAL-type AND-OR sum-of-products, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| Bidirectional I/O Pins | 24 | β |
| Total Inputs to Logic Array | 36 | β |
| Product Terms | 240 maximum | β |
| Maximum Propagation Delay (tPD) | 40 ns | β |
| Maximum Operating Frequency (fMAX) | 25 MHz | β |
| Global Clocks | 2 | β |
| Supply Voltage | 5 V (typical for Classic EPLD family) | 5 V |
| Operating Temperature (Commercial) | 0 Β°C to 70 Β°C | β |
| Package | DIP-40 (ceramic, through-hole) | DIP-40 (through-hole, 600 mil) |
| Mounting Type | Through-Hole | Through-Hole |
| RoHS Status | [DATA_NEEDED: rohs_status] | β |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | UV-Erasable / OTP |
| Family | β | Classic EPLD (EP910 series) |
| Gate Count | β | 900 usable gates |
| Propagation Delay (tPD) | β | 30 ns (max) |
| Clock Frequency (fCNT) | β | 33.3 MHz |
| Outputs (Macrocells) | β | 24 |
| External Clock Pins | β | 2 (CLK1, CLK2) |
| Process Technology | β | CMOS |
| Operating Temperature | β | 0C to +70C (commercial) |