EP910DI-30 vs EP910DC-40 Comparison
Detailed side-by-side comparison of EP910DI-30 by Rochester Electronics and EP910DC-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndSpecification Comparison
| Parameter | EP910DI-30 | EP910DC-40 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.60 | $13.95 |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | β |
| Family | Classic EPLD (Altera EP910 series) | β |
| Macrocell Count | 24 | β |
| Propagation Delay (tpd) | 30 ns | β |
| Maximum Toggle Frequency (fmax) | 62 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | β |
| Technology | CMOS, UV-erasable EPROM | β |
| Package | CDIP-40 (ceramic DIP, 40-pin with UV window) | DIP-40 (ceramic, through-hole) |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 (12 input + 12 output) | β |
| Output Enable Pins | 2 | β |
| Pin Count | 40 | β |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | β |
| Operating Temperature | -40C to +85C (industrial) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs_status] |
| Manufacturer (Original) | Altera (now Intel PSG) | β |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | β |
| Device Family | β | Classic EPLD (EP910 series) |
| Architecture | β | PAL-type AND/OR, UV-erasable CMOS |
| Macrocells | β | 24 |
| Bidirectional I/O Pins | β | 24 |
| Total Inputs to Logic Array | β | 36 |
| Product Terms | β | 240 maximum |
| Maximum Propagation Delay (tPD) | β | 40 ns |
| Maximum Operating Frequency (fMAX) | β | 25 MHz |
| Global Clocks | β | 2 |
| Supply Voltage | β | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | β | 0 Β°C to 70 Β°C |
| Programming Method | β | UV-erase + EPROM programmer; on-board logic test circuitry |