EP910DI-35 vs EP910IDI-15 Comparison
Detailed side-by-side comparison of EP910DI-35 by Altera and EP910IDI-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DI-35 | EP910IDI-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $35.20 | $29.00 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | β |
| Propagation Delay (tPD) | 35 ns | β |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | β |
| Supply Current (ICC) | 40 mA typical | β |
| Dedicated Inputs | 10 | β |
| Bidirectional I/O Pins | 20 | β |
| Total Pins | 40 | β |
| Package | CDIP-40 (Ceramic DIP with UV window) | 40-pin CDIP (CerDIP) with quartz window |
| Mounting Type | Through-Hole | Through-hole (DIP) |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial, "I" grade) |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| Programming Method | EPROM programmer + JEDEC fuse map | β |
| Erasure Method | UV light through quartz window | β |
| RoHS Status | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Logic Family | PAL-type AND/OR array with D flip-flops | β |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Gates | β | 450 gates |
| Maximum User I/O Pins | β | 36 |
| Pin-to-Pin Propagation Delay (tpd) | β | 15 ns |
| Maximum Counter Frequency | β | 66.6 MHz |
| Supply Voltage (Vcc) | β | 5 V |
| Program/Erase Method | β | UV-erasable windowed CerDIP |
| Macrocells Configurable As | β | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | β | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | β | Altera Logic Programmer card |
| Logic Family Compatibility | β | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |