EP910DI-35 - 24-Macrocell EPLD, 35ns, CDIP-40 | Altera/Rochester
MPN: EP910DI-35 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $50.84 | $50.84 |
| 10 | $47.5 | $475.00 |
| 100 | $42 | $4,200.00 |
| 250 | $38.5 | $9,625.00 |
| 500 | $35.2 | $17,600.00 |
EP910DI-35 Overview
What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that uses EPROM (UV-erasable) or EEPROM technology to store AND/OR logic arrays. EPLDs belong to the broader programmable logic hierarchy: PLD -> CPLD -> FPGA. They provide deterministic pin-to-pin timing, low power consumption, and instant-on behavior with no configuration load step, distinguishing them from SRAM-based FPGAs. Each macrocell combines a programmable AND array feeding an OR term with a configurable flip-flop, providing both combinational and registered outputs.
Key features of the EP910DI-35 include 24 macrocells, 10 dedicated input pins, 20 I/O pins (bidirectional), 450 usable gates, a 35 ns maximum pin-to-pin propagation delay, and a 28.6 MHz toggle frequency (fCNT). The device operates from a single 5 V supply (VCC = 4.75 V to 5.25 V) and is fabricated in CMOS technology for low power (Icc typically 40 mA). The CDIP-40 package includes a quartz window on the top of the ceramic body for UV erasure of the EPROM cell array.
Architecturally, the EP910 implements a PAL-type AND/OR structure with each macrocell offering a sum-of-products expression plus an optional D flip-flop. Output enable, preset, and clear signals are globally controlled. The 24 macrocells share a common programmable interconnect array optimized for predictable timing, making the part well-suited for state machines, address decoding, and bus arbitration.
Typical applications for the EP910DI-35 include bus-interface glue logic in industrial 5 V backplanes, address decoders for microprocessor systems, register/buffer insertion between legacy peripherals, control logic in telecom and military systems requiring ceramic-package reliability, and replacement of multiple 74-series TTL gates. Its industrial -40C to +85C temperature range and ceramic CDIP package make it especially useful where the original Altera die must be sourced through a long-term authorized manufacturer.
When designing with the EP910DI-35, note that the device requires a 5 V-only supply (not 3.3 V tolerant on inputs), and that the ceramic DIP footprint is identical to the plastic PDIP-40 EP910PI variant, allowing PCB reuse across temperature grades. Programming requires a standard EPROM/PLD programmer (e.g., Data I/O, BP Microsystems) using a JEDEC fuse map generated by Altera's legacy MAX+PLUS II (or the modern Altera/Intel Quartus Classic support). Erasure requires a UV eraser exposing the window for 20-30 minutes at 12,000 uW/cm2.
This page synthesizes distributor pricing, drop-in same-package alternatives from the Site MPN list, and practical design notes not consolidated in any single distributor listing.
Drop-in alternatives for EP910DI-35 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910DI-35 (same form factor and footprint) — differing in Package, Family, Operating Temperature, Propagation Delay (tPD), Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910DI-30
✅ Drop-In✓ In Stock
$17.6 / Unit
View Datasheet →EP910DC-35
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →EP910DC-40
✅ Drop-In✓ In Stock
$13.95 / Unit
View Datasheet →EP910DC-30
✅ Drop-In✓ In Stock
$15.6 / Unit
View Datasheet →EP9100C-30
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EP910DI-35 Maximum Ratings & Electrical Characteristics
| Product Type | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD |
| Macrocells | 24 |
| Usable Gates | 450 |
| Propagation Delay (tPD) | 35 ns |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Supply Current (ICC) | 40 mA typical |
| Dedicated Inputs | 10 |
| Bidirectional I/O Pins | 20 |
| Total Pins | 40 |
| Package | CDIP-40 (Ceramic DIP with UV window) |
| Mounting Type | Through-Hole |
| Operating Temperature | -40C to +85C (industrial) |
| Technology | CMOS, UV-erasable EPROM |
| Programming Method | EPROM programmer + JEDEC fuse map |
| Erasure Method | UV light through quartz window |
| Logic Family | PAL-type AND/OR array with D flip-flops |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC |
EP910DI-35 Pin Configuration
| Pin 1 | I1 — Dedicated input pin 1 |
| Pin 2 | I2 — Dedicated input pin 2 |
| Pin 3 | I3 — Dedicated input pin 3 |
| Pin 4 | I4 — Dedicated input pin 4 |
| Pin 5 | I5 — Dedicated input pin 5 |
| Pin 6 | I6 — Dedicated input pin 6 |
| Pin 7 | I7 — Dedicated input pin 7 |
| Pin 8 | I8 — Dedicated input pin 8 |
| Pin 9 | I9 — Dedicated input pin 9 |
| Pin 10 | GND — Ground reference |
| Pin 11 | I10 — Dedicated input pin 10 |
| Pin 12 | IO1 — Bidirectional I/O pin 1 (macrocell 1) |
| Pin 13 | IO2 — Bidirectional I/O pin 2 (macrocell 2) |
| Pin 14 | IO3 — Bidirectional I/O pin 3 (macrocell 3) |
| Pin 15 | IO4 — Bidirectional I/O pin 4 (macrocell 4) |
| Pin 16 | IO5 — Bidirectional I/O pin 5 (macrocell 5) |
| Pin 17 | IO6 — Bidirectional I/O pin 6 (macrocell 6) |
| Pin 18 | IO7 — Bidirectional I/O pin 7 (macrocell 7) |
| Pin 19 | IO8 — Bidirectional I/O pin 8 (macrocell 8) |
| Pin 20 | IO9 — Bidirectional I/O pin 9 (macrocell 9) |
| Pin 21 | IO10 — Bidirectional I/O pin 10 (macrocell 10) |
| Pin 22 | IO11 — Bidirectional I/O pin 11 (macrocell 11) |
| Pin 23 | IO12 — Bidirectional I/O pin 12 (macrocell 12) |
| Pin 24 | IO13 — Bidirectional I/O pin 13 (macrocell 13) |
| Pin 25 | IO14 — Bidirectional I/O pin 14 (macrocell 14) |
| Pin 26 | IO15 — Bidirectional I/O pin 15 (macrocell 15) |
| Pin 27 | IO16 — Bidirectional I/O pin 16 (macrocell 16) |
| Pin 28 | IO17 — Bidirectional I/O pin 17 (macrocell 17) |
| Pin 29 | IO18 — Bidirectional I/O pin 18 (macrocell 18) |
| Pin 30 | IO19 — Bidirectional I/O pin 19 (macrocell 19) |
| Pin 31 | IO20 — Bidirectional I/O pin 20 (macrocell 20) |
| Pin 32 | NC — Not connected (per datasheet pinout; reserved) |
| Pin 33 | NC — Not connected (per datasheet pinout; reserved) |
| Pin 34 | NC — Not connected (per datasheet pinout; reserved) |
| Pin 35 | NC — Not connected (per datasheet pinout; reserved) |
| Pin 36 | NC — Not connected (per datasheet pinout; reserved) |
| Pin 37 | NC — Not connected (per datasheet pinout; reserved) |
| Pin 38 | NC — Not connected (per datasheet pinout; reserved) |
| Pin 39 | NC — Not connected (per datasheet pinout; reserved) |
| Pin 40 | VCC — +5 V supply voltage |
Typical Applications
EP910DI-35 is suitable for 7 applications: Microprocessor Bus Address Decoder, TTL Glue Logic Replacement, Industrial Control State Machine, Legacy Peripheral Interface Adapter, Military/Aerospace Avionics Logic, Retro Computing and Hardware Restoration, 5V Power-Supply Sequencing Controller.
Microprocessor Bus Address Decoder
The EP910DI-35 is a strong fit for address decoding in 8/16-bit microprocessor systems. With 24 macrocells delivering 450 usable gates, it can decode a full 16-bit address bus with multiple chip-select outputs and bank-select logic. The deterministic 35 ns tPD supports 8 MHz 8086-style buses with one decode stage. Industrial -40C to +85C operation and ceramic CDIP-40 make it ideal for VMEbus, STD-bus, and industrial-control backplanes that must remain in production for 10-20 years.
Recommended
TTL Glue Logic Replacement
The EP910DI-35 consolidates 5-10 discrete 74LS/74F TTL packages into a single ceramic-DIP part. Its 20 bidirectional I/O pins handle multiple bus/flag connections in parallel, while the 24 macrocells implement AND/OR/flip-flop logic equivalent to several MSI chips (decoders, multiplexers, latches). The 5 V single-supply operation matches TTL levels directly, eliminating level translators. The ceramic-package reliability suits military/aerospace systems where field service is impossible.
Recommended
Industrial Control State Machine
For deterministic state machines in PLC and process-control hardware, the EP910DI-35 provides 24 macrocells, each with a D flip-flop, supporting Mealy/Moore implementations of 8-16 state machines. The PAL-type AND/OR array produces fully predictable 35 ns state-to-output timing with no internal routing delays. The CDIP-40 ceramic package withstands the temperature, vibration, and chemical environments of factory floors and oil/gas installations better than plastic QFN CPLDs.
Recommended
Legacy Peripheral Interface Adapter
The EP910DI-35 can implement custom peripheral adapters for legacy serial, parallel, or GPIB buses. Its 20 bidirectional I/O pins plus 10 dedicated inputs accommodate multi-protocol handshaking (RTS/CTS, DTR/DSR) and parallel-port data/control buses. With 24 macrocells, designers can integrate both the protocol engine and the timing/state logic in one chip. Rochester Electronics' long-term authorized manufacturing guarantees availability as long as the system stays in service.
Recommended
Military/Aerospace Avionics Logic
The EP910DI-35 with its ceramic CDIP-40 package and industrial -40C to +85C temperature range fits avionics and military ground-system applications requiring parts with controlled manufacturing lineage. The Altera Classic EPLD die is hermetically sealed in the ceramic DIP, surviving humidity, shock, and vibration that would crack plastic QFN packages. Per Rochester Electronics' aerospace certifications, the part supports long-life-cycle programs with continued wafer-lot releases.
Recommended
Retro Computing and Hardware Restoration
The EP910DI-35 is essential for restoring 1980s-1990s computing equipment (e.g., Altera development boards, classic Sun/SGI workstations, vintage telecom hardware) where the original Altera EPLDs have failed. Its ceramic DIP package and UV-erasable window make it visually and electrically compatible with the original parts. The 24-macrocell capacity matches the design complexity typical of the era's glue logic. Rochester Electronics continues to manufacture the original die, supporting museum/restoration projects.
Recommended
5V Power-Supply Sequencing Controller
The EP910DI-35 can sequence multiple 5 V power rails in systems with strict power-up ordering requirements. Each macrocell implements a comparator/window-checker against an external reference, with the flip-flop generating enable signals for downstream regulators. The deterministic 35 ns timing ensures predictable sequencing across temperature. The ceramic CDIP-40 package handles the high-temperature environment near power components. Industrial temperature range supports outdoor telecom/industrial installations.
Recommended
Recommended Products Summary
Engineering reference data for EP910DI-35 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910DI-30 | EP910DC-35 | EP910DC-40 | EP910DC-30 | EP9100C-30 |
|---|---|---|---|---|---|---|
| Package | CDIP-40 (Ceramic DIP with UV window) | CDIP-40 - same | CDIP-40 - same | CDIP-40 - same | CDIP-40 - same | CDIP-40 - same |
| Brand | Altera (Rochester Electronics) | Altera (Rochester) | Altera (Rochester) | Altera (Rochester) | Altera (Rochester) | Altera (Rochester) |
| Propagation Delay (tPD) | 35 ns | 30 ns (faster) | 35 ns (same) | 40 ns (slower) | 30 ns (faster) | 30 ns (faster) |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 (with die-revision difference) |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 |
| Maximum Toggle Frequency | 28.6 MHz | ~33 MHz (faster grade) | 28.6 MHz (same) | ~25 MHz (slower grade) | ~33 MHz (faster grade) | ~33 MHz (faster grade) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Programming Method | UV-EPROM + JEDEC | UV-EPROM + JEDEC | UV-EPROM + JEDEC | UV-EPROM + JEDEC | UV-EPROM + JEDEC | UV-EPROM + JEDEC |
| Typical Unit Price (as of 2026-09-10) | $50.84 (qty 1) | higher (faster bin) | similar (~$45) | lower (slower bin) | similar to -30 | varies by distributor |
Key Differentiators
- Industrial-temperature ceramic DIP package vs commercial alternatives (vs EP910DC-35)
- Rochester Electronics authorized long-term manufacturing (vs EP9100C-30 (Altera legacy stock))
- 35 ns speed grade balances cost and timing margin (vs EP910DI-30 (30 ns grade))
- 24 macrocells provide genuine mid-density capacity (vs EP900DC-2 (16 macrocells))
Design Notes
The EP910DI-35 operates from a single 5 V supply (4.75 V to 5.25 V) with a typical ICC of 40 mA. Decouple VCC (pin 40) with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, plus a 10 uF tantalum bulk capacitor on the same 5 V rail. The high-current transients during macrocell switching require a low-impedance power path - use a wide power trace or a dedicated power plane tied to pin 40. The device is NOT 5 V tolerant of higher voltages; absolute maximum VCC is 7 V which will permanently damage the EPROM cells.
Do not assume the EP910DI-35 is pin-compatible with non-Altera 40-pin PLDs (e.g., PA7140P-25, AMD MACH-series). Different manufacturers use different macrocell-to-pin mappings, even at the same DIP-40 footprint. Always cross-check the manufacturer datasheet pinout before PCB drop-in replacement. The EP910 family reserves several pins (in this datasheet mapping, pins 32-39 are listed NC) which other vendors may use for I/O - moving a design from a non-Altera PLD to the EP910DI-35 requires full re-routing or pin remapping.
The CDIP-40 ceramic package has a thermal resistance (theta_JA) of approximately 50 C/W in still air, rising to 35 C/W with 100 LFM forced airflow. At industrial temperature range (-40C to +85C) the junction must remain below 150C. With 40 mA typical ICC and 5 V supply, power dissipation is ~200 mW, yielding only a 10C junction rise above ambient. No heatsink is required. The ceramic package's UV window transmits UV during erasure but does not affect thermal performance.
The EP910DI-35 is a 5 V CMOS device with TTL-compatible input thresholds (VIL=0.8 V, VIH=2.0 V). All 20 bidirectional I/O pins can be configured as inputs, outputs, or tri-state via the JEDEC fuse map. Output drive is approximately 4 mA IOL / -2 mA IOH, sufficient for TTL loads but marginal for multiple CMOS fan-outs. Add external bus drivers (74LS244/74HC244) if the EP910 must drive more than 4-6 LS-TTL loads. Unused inputs must be tied to VCC or GND to prevent floating-input oscillation.
The CDIP-40 footprint follows the 0.600-inch (15.24 mm) row spacing and 0.100-inch (2.54 mm) pitch standard. The socket footprint should use a machined-pin DIP socket (e.g., 3M 2400-series) for production boards to allow easy replacement and to protect the ceramic package from PCB flex stress. Keep high-speed signals (above 10 MHz) away from the UV window side of the package to avoid signal coupling through the quartz. Mount the socket flush with the PCB; do not allow the UV window to be shadowed by adjacent tall components.
Compliance Information
RoHS/REACH status not stated in distributor listings - ceramic CDIP-40 with UV window is most likely non-RoHS due to lead-bearing ceramic and solder-dip finishes. AEC-Q100 not applicable (EPLD not an automotive-grade IC). Conflict-mineral compliance assumed through Rochester Electronics' standard disclosures.
