EP910DM-40 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910DM-40 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DM-40 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.00 | $15.60 |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | β |
| Family | Altera Classic EP910 | Classic EPLD (EP910 series) |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | PAL-type AND-OR sum-of-products, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | 36 |
| Dedicated Outputs | 24 | β |
| Bidirectional I/O Lines | 24 | β |
| Product Terms | 240 | β |
| Propagation Delay (tPD) | 40 ns | 30 ns (max) |
| External Clocks | 2 | β |
| Process Technology | CMOS | CMOS |
| Package | 40-pin Ceramic DIP (Cerdip) with UV window | DIP-40 (through-hole, 600 mil) |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Supply Voltage | 5 V | 5 V |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | β |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | β |
| Gate Count | β | 900 usable gates |
| Clock Frequency (fCNT) | β | 33.3 MHz |
| Outputs (Macrocells) | β | 24 |
| External Clock Pins | β | 2 (CLK1, CLK2) |
| Programming Method | β | UV-Erasable / OTP |