EP910IDC-15 vs EP910DC-35 Comparison

Detailed side-by-side comparison of EP910IDC-15 by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910IDC-15 EP910DC-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $10.95
Manufacturer Altera (now Intel PSG) β€”
Family Classic EPLD Classic EPLD EP910
Equivalent Gates 450 β€”
Macrocells 24 24
Flip-Flops 48 β€”
Pin-to-Pin Delay (tPD) 15 ns β€”
Maximum Frequency (fCNT) 66.6 MHz β€”
Supply Voltage (VCC) 5 V β€”
Package 40-pin CDIP (Ceramic DIP, through-hole) 40-pin CDIP (Ceramic DIP) with quartz window
Terminal Count 40 β€”
Terminal Form Through-Hole β€”
Temperature Grade Commercial (0C to +70C) β€”
Programmable Security Bit Yes β€”
On-board Test Circuitry Yes β€”
Logic Type UV Erasable EPROM-based β€”
I/O Pins 24 24
Dedicated Inputs 10 12
Programming Technology EPROM (UV-erasable) β€”
RoHS Status non_compliant (ceramic DIP contains lead) Non-compliant (ceramic DIP with Pb-bearing lead finish)
Device Type β€” UV-Erasable CMOS PLD (PAL-type)
Architecture β€” PAL-type sum-of-products AND-OR array
Usable Gates β€” 900 gates
Product Terms β€” 240
Total Inputs β€” 36
Propagation Delay (tpd) β€” 35 ns
Maximum Clock Frequency β€” 37 MHz (typical, internal)
Supply Voltage (Vcc) β€” 4.75 V to 5.25 V (5 V nominal)
Operating Temperature β€” 0 Β°C to +70 Β°C (commercial)
Lead Pitch β€” 2.540 mm
Termination Style β€” Through-Hole
Programming Method β€” JEDEC fuse map via device programmer; UV erase
Technology β€” CMOS, UV-erasable EPROM cell
Lifecycle β€” Obsolete / last-time-buy from authorized distributors

Datasheets & Resources

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