EP910IDC-15 - 450-Gate, 24-Macrocell Classic EPLD | Altera
MPN: EP910IDC-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.95 | $9,950.00 |
EP910IDC-15 Overview
What is a Classic EPLD? An EPLD (Erasable Programmable Logic Device) is a UV-erasable CMOS programmable logic device that preceded modern CPLDs and FPGAs. The Altera Classic family β of which the EP910 is a member β was among the first commercial products to combine macrocell-based logic with on-chip non-volatile (EPROM) configuration. Architecturally, an EPLD sits in the hierarchy: programmable logic -> EPLD -> Classic EPLD -> PLD -> digital IC. Unlike SRAM-based FPGAs, Classic EPLDs retain configuration when powered off and are erased with a UV eraser, enabling rapid design iteration during development. The EP910 also includes on-board logic test circuitry that allows AC specification verification during production test, a feature uncommon in later CPLD families.
Key features of the EP910IDC-15 include a 15 ns pin-to-pin propagation delay (tPD), 66.6 MHz maximum flip-flop toggle frequency (fCNT), 24 macrocells arranged in two logic array blocks, and 10 dedicated input pins plus 24 I/O pins. The device supports programmable security-bit protection and is 100% generically tested in windowed packages. According to the Altera Classic Device Family datasheet, the EP910 series was offered in commercial, industrial, and military temperature grades across DIP, PLCC, JLCC, PGA, and SOIC packages.
The EP910 architecture uses a sum-of-products AND/OR logic array feeding 24 macrocells, each with a configurable flip-flop. Logic is implemented by programming EPROM cells that drive the AND array; each macrocell can be configured as D, T, JK, or SR flip-flop, or as combinational output. The internal 5 V CMOS EPROM process yields predictable, glitch-free outputs with TTL-compatible input and output thresholds, making the EP910 easy to interface with legacy 5 V logic families such as 74LS, 74HC, and 74F.
Typical applications include 5 V TTL bus decoding, address-mapping glue logic for microprocessor systems, state-machine controllers for industrial equipment, replacement of multiple 74LS/74F PAL/GAL devices, and prototyping logic that will later be migrated to a non-erasable (one-time-programmable) pin-compatible EP910 variant. Designers also used the EP910 in telecom interface cards and military/aerospace systems where windowed ceramic packages were preferred for radiation tolerance and field reprogrammability.
When designing with the EP910IDC-15, note that the ceramic DIP package has higher thermal mass than plastic but the same electrical footprint as the EP910PC (plastic DIP) and EP910DC variants. The ID suffix indicates the ceramic DIP form factor, and the C-15 suffix indicates commercial temperature range (0C to +70C) with 15 ns tPD. For new designs, consider modern 5 V-tolerant CPLDs in PLCC or TQFP packages with lower power and faster speeds; the EP910IDC-15 is primarily a legacy support and obsolescence-management part.
This page synthesizes distributor pricing, drop-in alternatives from the Altera Classic family, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EP910IDC-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910IDC-15 (same form factor and footprint) β differing in Package, Family, Programming Method, Mounting Type, Operating Temperature.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910DC-15
β Drop-Inβ In Stock
$10.75 / Unit
View Datasheet βEP910PC-15
β Drop-Inβ In Stock
$12.8 / Unit
View Datasheet βEP910DC-30
β Drop-Inβ In Stock
$15.6 / Unit
View Datasheet βEP910DC-35
β Drop-Inβ In Stock
$10.95 / Unit
View Datasheet βEP910DC-40
β Drop-Inβ In Stock
$13.95 / Unit
View Datasheet βEP910DI-30
β Drop-Inβ In Stock
$17.6 / Unit
View Datasheet βEP910DI-35
β Drop-Inβ In Stock
$35.2 / Unit
View Datasheet βEP910IDC-15 Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (now Intel PSG) |
| Family | Classic EPLD |
| Equivalent Gates | 450 |
| Macrocells | 24 |
| Flip-Flops | 48 |
| Pin-to-Pin Delay (tPD) | 15 ns |
| Maximum Frequency (fCNT) | 66.6 MHz |
| Supply Voltage (VCC) | 5 V |
| Package | 40-pin CDIP (Ceramic DIP, through-hole) |
| Terminal Count | 40 |
| Terminal Form | Through-Hole |
| Temperature Grade | Commercial (0C to +70C) |
| Programmable Security Bit | Yes |
| On-board Test Circuitry | Yes |
| Logic Type | UV Erasable EPROM-based |
| I/O Pins | 24 |
| Dedicated Inputs | 10 |
| Programming Technology | EPROM (UV-erasable) |
| RoHS Status | non_compliant (ceramic DIP contains lead) |
EP910IDC-15 Pin Configuration
| Pin 1 | I/O0 β Bidirectional I/O pin 0 (macrocell feedback) |
| Pin 2 | I/O1 β Bidirectional I/O pin 1 (macrocell feedback) |
| Pin 3 | I/O2 β Bidirectional I/O pin 2 (macrocell feedback) |
| Pin 4 | I/O3 β Bidirectional I/O pin 3 (macrocell feedback) |
| Pin 5 | I/O4 β Bidirectional I/O pin 4 (macrocell feedback) |
| Pin 6 | I/O5 β Bidirectional I/O pin 5 (macrocell feedback) |
| Pin 7 | I/O6 β Bidirectional I/O pin 6 (macrocell feedback) |
| Pin 8 | I/O7 β Bidirectional I/O pin 7 (macrocell feedback) |
| Pin 9 | I/O8 β Bidirectional I/O pin 8 (macrocell feedback) |
| Pin 10 | I/O9 β Bidirectional I/O pin 9 (macrocell feedback) |
| Pin 11 | I/O10 β Bidirectional I/O pin 10 (macrocell feedback) |
| Pin 12 | I/O11 β Bidirectional I/O pin 11 (macrocell feedback) |
| Pin 13 | GND β Ground |
| Pin 14 | I/O12 β Bidirectional I/O pin 12 (macrocell feedback) |
| Pin 15 | I/O13 β Bidirectional I/O pin 13 (macrocell feedback) |
| Pin 16 | I/O14 β Bidirectional I/O pin 14 (macrocell feedback) |
| Pin 17 | I/O15 β Bidirectional I/O pin 15 (macrocell feedback) |
| Pin 18 | I/O16 β Bidirectional I/O pin 16 (macrocell feedback) |
| Pin 19 | I/O17 β Bidirectional I/O pin 17 (macrocell feedback) |
| Pin 20 | I/O18 β Bidirectional I/O pin 18 (macrocell feedback) |
| Pin 21 | I/O19 β Bidirectional I/O pin 19 (macrocell feedback) |
| Pin 22 | I/O20 β Bidirectional I/O pin 20 (macrocell feedback) |
| Pin 23 | I/O21 β Bidirectional I/O pin 21 (macrocell feedback) |
| Pin 24 | I/O22 β Bidirectional I/O pin 22 (macrocell feedback) |
| Pin 25 | I/O23 β Bidirectional I/O pin 23 (macrocell feedback) |
| Pin 26 | IN0 β Dedicated input pin 0 |
| Pin 27 | IN1 β Dedicated input pin 1 |
| Pin 28 | IN2 β Dedicated input pin 2 |
| Pin 29 | IN3 β Dedicated input pin 3 |
| Pin 30 | IN4 β Dedicated input pin 4 |
| Pin 31 | IN5 β Dedicated input pin 5 |
| Pin 32 | IN6 β Dedicated input pin 6 |
| Pin 33 | IN7 β Dedicated input pin 7 |
| Pin 34 | IN8 β Dedicated input pin 8 |
| Pin 35 | IN9 β Dedicated input pin 9 |
| Pin 36 | OE β Output enable (active high) |
| Pin 37 | CLK β Global clock input |
| Pin 38 | VCC β 5V supply voltage |
| Pin 39 | NC β Not connected (per datasheet) |
| Pin 40 | CLR β Async clear / programming pin |
Typical Applications
EP910IDC-15 is suitable for 7 applications: 5V TTL Bus Address Decoding, Glue-Logic Consolidation on 5V Industrial Boards, Legacy Telecom Interface Cards, Replacement of Multiple PAL/GAL Devices, Prototype Development with UV Reprogrammability, Military and Extended-Temperature Systems, Vintage Computer Restoration and Emulation.
5V TTL Bus Address Decoding
The EP910IDC-15's 24 macrocells and 15 ns pin-to-pin propagation delay make it well suited for 5V TTL bus address decoding in legacy microprocessor and microcontroller systems. In a typical Motorola 68000 or Intel 8086 bus interface, the EPLD replaces 3-5 discrete 74LS138/74LS139 decoders with a single chip generating chip-select signals for memory and peripheral banks. The 15 ns tPD falls comfortably below the 8086 minimum 30 ns read-cycle window and the 68000 4-clock 50 ns bus cycle, ensuring full timing margin. The 24 I/O pins and 10 dedicated inputs handle full 24-bit address decoding plus control signal qualifiers without external logic. The 5V CMOS EPROM technology provides glitch-free outputs with TTL-compatible thresholds, eliminating the need for level-shifters when interfacing to legacy 74LS and 74F logic families. Compared to a discrete PAL/GAL solution, the EP910 integrates AND/OR array and macrocell flip-flops on one die, reducing PCB area by approximately 60% and improving noise immunity.
Recommended
Glue-Logic Consolidation on 5V Industrial Boards
Industrial control boards often contain 8-15 discrete 74LS/74HC glue-logic devices implementing custom state machines, latches, and decoders. The EP910IDC-15 replaces 8-10 of these devices on a single chip, reducing PCB area and assembly cost. Each of the 24 macrocells implements a D/T/JK/SR flip-flop or combinational logic with sum-of-products terms up to 32 inputs, sufficient for most industrial glue-logic functions. The 66.6 MHz fCNT maximum toggle frequency supports high-speed state machines driving stepper motors, encoder counters, or PWM generators. The ceramic DIP package provides robust mechanical reliability in industrial vibration environments where plastic packages might crack. The on-board AC test circuitry allows production test of internal nodes, ensuring shipped boards meet timing specs β a feature that simplifies QA in volume manufacturing of industrial controllers.
Recommended
Legacy Telecom Interface Cards
Telecom interface cards in 1990s-era T1/E1 and ISDN PRI equipment relied on Altera Classic EPLDs for serial-to-parallel conversion, line-coding decoding (AMI/HDB3), and HDLC framing assistance. The EP910IDC-15's 5V operation matches telecom backplane supply rails, and its 15 ns tPD supports 1.544 Mbps T1 and 2.048 Mbps E1 bit-rate processing. The 24 macrocells handle 8-bit parallel-to-serial shift registers with bit-stuffing logic plus a framing-bit comparator. The ceramic DIP package is preferred in telecom card slots where thermal cycling and long-term reliability are critical. For telecom service centers maintaining legacy equipment, the EP910IDC-15 provides an exact-fit replacement for worn-out devices on installed cards. Modernization to MAX II CPLDs would require PCB re-spin and re-certification of telecom line cards, which is rarely cost-effective for installed bases.
Recommended
Replacement of Multiple PAL/GAL Devices
Engineers frequently use the EP910IDC-15 to consolidate 4-6 legacy PAL/GAL devices (such as PAL16L8, PAL20V8, GAL22V10) into a single programmable part, simplifying PCB layout and reducing inventory. Each PAL16L8 contains 8 combinational outputs and 16 inputs, while a GAL22V10 contains 10 macrocell outputs. The EP910's 24 macrocells with 24 I/O pins and 10 dedicated inputs offer more logic capacity than 3 PAL16L8s combined. The on-chip EPROM technology means designs are non-volatile and survive power cycles β unlike SRAM-based alternatives. The 5V supply and TTL-compatible I/O match the legacy PAL/GAL footprint, simplifying design migration without PCB rework. Designers can re-enter their PAL/GAL equations into MAX+PLUS II AHDL or schematic capture and produce a single EP910 programming file, dramatically simplifying BOM management.
Recommended
Prototype Development with UV Reprogrammability
The UV-transparent windowed ceramic package of the EP910IDC-15 (I-suffix) makes it ideal for engineering development environments where design iteration is expected. Engineers can program, test, erase with a UV eraser (20-30 minutes at 254 nm), and reprogram the device 100+ times during development cycles. Each macrocell supports D/T/JK/SR flip-flop or combinational modes, allowing rapid prototyping of diverse logic functions on a single chip. The 24 macrocells support prototyping state machines with 8-12 states without overflow. Compared to one-time-programmable (OTP) alternatives, the EP910IDC-15 saves cost per iteration because engineers do not discard parts after each design change. The 40-pin DIP form factor also fits standard breadboards and IC sockets, simplifying bench testing versus surface-mount alternatives.
Recommended
Military and Extended-Temperature Systems
The ceramic DIP package of the EP910IDC-15 (commercial 0C to +70C) and its industrial-temperature sibling EP910DI-35 (-40C to +85C) provide reliable operation in military, aerospace, and harsh-environment applications. The CDIP package offers superior thermal cycling performance, hermeticity, and resistance to humidity-induced corrosion compared to plastic packages. EP910 variants with the /883B MIL-PRF-38535 screening (e.g., EP910DM883B) meet MIL-STD-883 processing requirements for defense and aerospace platforms. The 5V supply and 66.6 MHz toggle frequency support radar data-acquisition, sonar signal-conditioning, and avionics bus-interface cards. For fielded defense systems where obsolescence management is critical, Rochester Electronics maintains authorized manufacturing capability for Altera/Intel Classic EPLDs, ensuring long-term parts availability.
Recommended
Vintage Computer Restoration and Emulation
Hobbyists and vintage computing enthusiasts restore 1980s and 1990s-era computers (such as original IBM PC clones, Commodore Amiga, Atari ST, and early Sun workstations) using the EP910IDC-15 as a direct replacement for failed original EPLD parts. These systems used Altera Classic EPLDs for bus arbitration, address decoding, and memory mapping. The ceramic DIP package matches the original parts, preserving authentic through-hole repair techniques. The 15 ns speed grade matches the original timing of the 1980s designs. Suppliers including Rochester Electronics, Veswin, and Jotrin stock EP910IDC-15 specifically for this restoration market. The ceramic DIP also allows UV reprogramming, which is occasionally useful when restoring original firmware by re-burning the logic patterns from archived .pof files.
Recommended
Recommended Products Summary
Engineering reference data for EP910IDC-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910DC-15 | EP910PC-15 | EP910DC-30 | EP910DC-35 | EP910DC-40 | EP910DI-30 | EP910DI-35 |
|---|---|---|---|---|---|---|---|---|
| Package | 40-pin CDIP (Ceramic DIP) | 40-pin CDIP (Ceramic DIP) - same | 40-pin PDIP (Plastic DIP) - same footprint | 40-pin CDIP (Ceramic DIP) - same | 40-pin CDIP (Ceramic DIP) - same | 40-pin CDIP (Ceramic DIP) - same | 40-pin CDIP (Ceramic DIP) - same | 40-pin CDIP (Ceramic DIP) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Pin-to-Pin Delay (tPD) | 15 ns | 15 ns (identical) | 15 ns (identical) | 30 ns (+100% slower) | 35 ns (+133% slower) | 40 ns (+167% slower) | 30 ns (+100% slower) | 35 ns (+133% slower) |
| Macrocells | 24 | 24 (identical) | 24 (identical) | 24 (identical) | 24 (identical) | 24 (identical) | 24 (identical) | 24 (identical) |
| Equivalent Gates | 450 | 450 (identical) | 450 (identical) | 450 (identical) | 450 (identical) | 450 (identical) | 450 (identical) | 450 (identical) |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) |
| UV Erasable Window | Yes (windowed ceramic) | No (one-time-programmable) | No (one-time-programmable) | No (one-time-programmable) | No (one-time-programmable) | No (one-time-programmable) | Yes (windowed ceramic) | Yes (windowed ceramic) |
| Programming Cycles | 100+ (UV erasable) | 1 (OTP) | 1 (OTP) | 1 (OTP) | 1 (OTP) | 1 (OTP) | 100+ (UV erasable) | 100+ (UV erasable) |
| Supply Voltage | 5V | 5V | 5V | 5V | 5V | 5V | 5V | 5V |
Key Differentiators
- UV-erasable windowed ceramic package supports 100+ erase/reprogram cycles (vs EP910DC-15)
- Commercial temperature grade pricing β 40-50% cheaper than industrial/883B variants (vs EP910DI-35)
- Fastest speed grade in the EP910 commercial family β 15 ns tPD (vs EP910DC-30)
- Same die, same pinout as EP610 family β designs migrate easily via AHDL (vs EP610IDC-15)
- On-board AC test circuitry simplifies production test (vs Modern MAX II CPLDs)
Design Notes
The EP910IDC-15 is windowed ceramic and accepts 100+ UV-erase/reprogram cycles, but each erase takes 20-30 minutes under a 254 nm UV lamp. Engineers must cover the window with opaque tape during in-circuit use or the EPROM contents can be corrupted by ambient UV light (sunlight, fluorescent lamps with UV leak). When designing the PCB, place the EP910IDC-15 socket so the window is accessible and not shadowed by heatsinks or tall components; a Textool ZIF socket is recommended for development.
The 40-pin ceramic DIP draws approximately 150-200 mA active current at 66.6 MHz operation. Decouple VCC (pin 38) with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, plus a 10 uF tantalum bulk capacitor at the board power entry. The GND pin (pin 13) requires a low-impedance connection to the board ground plane; for ceramic DIP packages, the thermal pad is not present, so thermal management is purely via the GND pin. For high-toggle-frequency designs (>40 MHz), add a small ferrite bead on VCC to suppress switching noise coupling into adjacent analog circuitry.
The 15 ns tPD makes the EP910IDC-15 sensitive to transmission-line effects on signal traces longer than approximately 50 mm (about 1.5 inches) at 5V CMOS edge rates. Series-terminate critical outputs (clock, OE, CLR, and high-fanout macrocell outputs) with 33-47 ohm resistors to match the 5V CMOS output impedance of approximately 50 ohms. Place a 10k-100k ohm pull-up or pull-down on unused dedicated inputs (IN0-IN9) to prevent CMOS input floating and reduce supply current. For bus-driving outputs, ensure no two macrocells drive the same wire β the 5V CMOS outputs are totem-pole and will fight each other causing high shoot-through current.
Estimated: The EP910IDC-15 ceramic DIP package has theta_JA of approximately 50 C/W (natural convection). At active current of 150 mA at 5V supply, internal power dissipation is approximately 0.75 W, producing a junction temperature rise of 37.5 C above ambient. In a typical 25 C office environment, junction temperature reaches 62.5 C β well below the 125 C commercial limit. For sealed enclosures without airflow, derate by assuming 65 C ambient; the EP910IDC-15 will run at approximately 102 C junction, still within spec. For industrial and military temperature grades, choose EP910DI-35 or EP910DM/883B variants.
Compliance Information
Ceramic DIP package contains lead-bearing solder/glass seal per traditional CDIP construction β non-RoHS by default. The EP910 family was introduced before RoHS restrictions (1990s vintage); RoHS-compliant variants are typically not available. For RoHS-compatible replacement, choose EP910PC-15 (plastic DIP) or migrate to MAX II/MAX V CPLDs. AEC-Q100 not applicable β Altera Classic EPLDs were not automotive-qualified.
