EP910IDI-15 vs EP910DC-15 Comparison

Detailed side-by-side comparison of EP910IDI-15 by Altera and EP910DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910IDI-15 EP910DC-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $29.00 $10.75
Family Classic EPLD Altera Classic EPLD
Device Type CPLD (Complex Programmable Logic Device) β€”
Logic Gates 450 gates β€”
Macrocells 24 24
Maximum User I/O Pins 36 β€”
Pin-to-Pin Propagation Delay (tpd) 15 ns β€”
Maximum Counter Frequency 66.6 MHz β€”
Supply Voltage (Vcc) 5 V β€”
Technology CMOS EPROM CMOS EPROM, UV-erasable
Program/Erase Method UV-erasable windowed CerDIP β€”
Package 40-pin CDIP (CerDIP) with quartz window 24-pin ceramic DIP (DC)
Operating Temperature -40C to +85C (industrial, "I" grade) 0C to +70C (commercial)
Mounting Type Through-hole (DIP) Through-Hole
Macrocells Configurable As D, T, JK, SR flip-flop, or combinatorial β€”
Development Tool MAX+PLUS II (legacy) / Altera Classic compiler β€”
Programming Hardware Altera Logic Programmer card β€”
RoHS Status [DATA_NEEDED: RoHS compliance of CDIP windowed part] [DATA_NEEDED: not explicitly stated in verified data]
Logic Family Compatibility Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages β€”
Device Density β€” 900 usable gates
Logic Elements β€” [DATA_NEEDED: exact LE count]
Dedicated Inputs β€” 12
Bidirectional I/O Pins β€” 12
Flip-Flops β€” 10
Product Terms per Macrocells β€” 24
Maximum Propagation Delay (tPD) β€” 15 ns
Speed Grade β€” 15
Supply Voltage (VCC) β€” 5 V (typical)
MSL Level β€” [DATA_NEEDED: MSL level]

Datasheets & Resources

Browse All Products Create BOM Request Quote