EP910IDI-15 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910IDI-15 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IDI-15 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $29.00 | $15.60 |
| Family | Classic EPLD | Classic EPLD (EP910 series) |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Logic Gates | 450 gates | β |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 36 | β |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns | β |
| Maximum Counter Frequency | 66.6 MHz | β |
| Supply Voltage (Vcc) | 5 V | β |
| Technology | CMOS EPROM | β |
| Program/Erase Method | UV-erasable windowed CerDIP | β |
| Package | 40-pin CDIP (CerDIP) with quartz window | DIP-40 (through-hole, 600 mil) |
| Operating Temperature | -40C to +85C (industrial, "I" grade) | 0C to +70C (commercial) |
| Mounting Type | Through-hole (DIP) | Through-Hole |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial | β |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler | β |
| Programming Hardware | Altera Logic Programmer card | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance of CDIP windowed part] | β |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages | β |
| Architecture | β | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | β | 900 usable gates |
| Propagation Delay (tPD) | β | 30 ns (max) |
| Clock Frequency (fCNT) | β | 33.3 MHz |
| Dedicated Inputs | β | 36 |
| Outputs (Macrocells) | β | 24 |
| External Clock Pins | β | 2 (CLK1, CLK2) |
| Supply Voltage | β | 5 V |
| Process Technology | β | CMOS |
| Programming Method | β | UV-Erasable / OTP |