EP910IDI-15 vs EP910DI-35 Comparison
Detailed side-by-side comparison of EP910IDI-15 by Altera and EP910DI-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IDI-15 | EP910DI-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $29.00 | $35.20 |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Logic Gates | 450 gates | β |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 36 | β |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns | β |
| Maximum Counter Frequency | 66.6 MHz | β |
| Supply Voltage (Vcc) | 5 V | β |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM |
| Program/Erase Method | UV-erasable windowed CerDIP | β |
| Package | 40-pin CDIP (CerDIP) with quartz window | CDIP-40 (Ceramic DIP with UV window) |
| Operating Temperature | -40C to +85C (industrial, "I" grade) | -40C to +85C (industrial) |
| Mounting Type | Through-hole (DIP) | Through-Hole |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial | β |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler | β |
| Programming Hardware | Altera Logic Programmer card | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance of CDIP windowed part] | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | β | 450 |
| Propagation Delay (tPD) | β | 35 ns |
| Maximum Toggle Frequency (fCNT) | β | 28.6 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (5 V nominal) |
| Supply Current (ICC) | β | 40 mA typical |
| Dedicated Inputs | β | 10 |
| Bidirectional I/O Pins | β | 20 |
| Total Pins | β | 40 |
| Programming Method | β | EPROM programmer + JEDEC fuse map |
| Erasure Method | β | UV light through quartz window |
| Logic Family | β | PAL-type AND/OR array with D flip-flops |
| Manufacturer | β | Original Altera; long-term authorized by Rochester Electronics, LLC |