EP910ILC-12 vs EP910DC-35 Comparison
Detailed side-by-side comparison of EP910ILC-12 by Intel and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910DC-35
EP910DC-35 - 35ns 900-Gate CMOS UV PLD DIP-40 | Intel / Altera
EP910DC-35 ObsoleteSpecification Comparison
| Parameter | EP910ILC-12 | EP910DC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.40 | $10.95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | β |
| Family | Altera EP910 Classic EPLD | Classic EPLD EP910 |
| Number of Macrocells | 24 | β |
| Usable Gates | 450 (typical) | 900 gates |
| Propagation Delay (tPD) | 12 ns (max) | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Nominal Supply | 5 V | β |
| Memory Technology | UV-erasable CMOS EPROM | β |
| Package | 28-PLCC (J-Lead, 11.5 x 11.5 mm) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Mounting Type | Surface Mount | β |
| Operating Temperature | -40 Β°C to +85 Β°C (industrial grade, 'I' suffix) | 0 Β°C to +70 Β°C (commercial) |
| Configuration Storage | Non-volatile EPROM (instant-on) | β |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) | JEDEC fuse map via device programmer; UV erase |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Number of Pins | 28 | β |
| Feedback Paths | 16 dedicated | β |
| Device Type | β | UV-Erasable CMOS PLD (PAL-type) |
| Architecture | β | PAL-type sum-of-products AND-OR array |
| Macrocells | β | 24 |
| Product Terms | β | 240 |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 |
| Total Inputs | β | 36 |
| Propagation Delay (tpd) | β | 35 ns |
| Maximum Clock Frequency | β | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | β | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | β | 2.540 mm |
| Termination Style | β | Through-Hole |
| Technology | β | CMOS, UV-erasable EPROM cell |
| Lifecycle | β | Obsolete / last-time-buy from authorized distributors |