EP910ILC-12 - 24-Macrocell 12ns Classic EPLD | Intel / Altera
MPN: EP910ILC-12 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $24.288 | $24.29 |
| 10 | $21.5 | $215.00 |
| 100 | $17.95 | $1,795.00 |
| 500 | $14.8 | $7,400.00 |
| 1,000 | $12.4 | $12,400.00 |
EP910ILC-12 Overview
A Classic EPLD (Erasable Programmable Logic Device) is an early-generation programmable logic device using UV-erasable CMOS architecture. EPLDs sit in the programmable logic hierarchy above discrete SSI/MSI gates but below modern CPLDs and FPGAs in density. They belong to the broader category of programmable logic ICs, sitting between PALs (Programmable Array Logic) and contemporary CPLD/FPGA devices. Each macrocell contains a programmable AND/OR array and a configurable flip-flop, allowing the chip to replace multiple discrete 74-series logic ICs on a board.
Key features include a 12 ns pin-to-pin propagation delay (tPD), 24 macrocells with 16 dedicated feedback paths, a 5 V ±5% supply range, and a JEDEC-standard 28-pin PLCC J-lead surface-mount package. The device is non-volatile - the logic configuration is stored in UV-erasable EPROM cells, providing instant-on behavior at power-up with no external boot memory required. The EP910 family is one of the longest-running Altera Classic EPLD families and is widely recognized for deterministic timing.
The EP910ILC-12 uses a CMOS EPROM-cell AND/OR plane feeding 24 output macrocells, each with a configurable flip-flop, output enable, and product-term steering. Programming is performed via a standard Altera programming algorithm using a master/slave serial or parallel mode. Because the configuration is non-volatile, there is no boot sequence, JTAG configuration, or bitstream loading - the part begins executing its logic immediately after VCC is stable.
Typical applications include glue-logic replacement in legacy 5 V systems, address decoding and bus-interface logic, state machines for industrial control boards, and prototyping replacements for discrete 74LS/74HC logic. The 12 ns tPD suits bus cycle times down to roughly 33 MHz, making it usable as a peripheral decoder in 8-bit and 16-bit microcontroller or 80x86 designs.
When designing with this device, note that the 'I' suffix indicates the industrial temperature grade (-40 °C to +85 °C) and the 'C' suffix indicates the PLCC J-Lead package. Programming requires a UV windowed ceramic device variant (not provided in the PLCC J-lead 'C' suffix used here) or a one-time-programmed plastic package. Verify programming toolchain and software version compatibility with the specific lot date code.
This page synthesizes distributor pricing, a drop-in replacement shortlist, and practical design notes not found in any single manufacturer datasheet, optimized for engineers sourcing legacy Classic EPLDs.
Drop-in alternatives for EP910ILC-12 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910ILC-12 (same form factor and footprint) — differing in Package, Family, Operating Temperature, Mounting Type, Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910ILC-15
✅ Drop-In✓ In Stock
$16.1 / Unit
View Datasheet →EP910IDC-15
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP910IDI-15
✅ Drop-In✓ In Stock
$29 / Unit
View Datasheet →EP910DC-15
✅ Drop-In✓ In Stock
$10.75 / Unit
View Datasheet →EP910DC-30
✅ Drop-In✓ In Stock
$15.6 / Unit
View Datasheet →EP910DC-35
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →EP910ILC-12 Maximum Ratings & Electrical Characteristics
| Product Type | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera EP910 Classic EPLD |
| Number of Macrocells | 24 |
| Usable Gates | 450 (typical) |
| Propagation Delay (tPD) | 12 ns (max) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Nominal Supply | 5 V |
| Memory Technology | UV-erasable CMOS EPROM |
| Package | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40 °C to +85 °C (industrial grade, 'I' suffix) |
| Configuration Storage | Non-volatile EPROM (instant-on) |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) |
| Number of Pins | 28 |
| Feedback Paths | 16 dedicated |
EP910ILC-12 Pin Configuration
| Pin 1 | I/O / OE — Macrocell I/O with output enable (configurable polarity) |
| Pin 2 | I/O — Macrocell input/output (bidirectional) |
| Pin 3 | I/O — Macrocell input/output (bidirectional) |
| Pin 4 | I/O — Macrocell input/output (bidirectional) |
| Pin 5 | I/O — Macrocell input/output (bidirectional) |
| Pin 6 | I/O — Macrocell input/output (bidirectional) |
| Pin 7 | I/O — Macrocell input/output (bidirectional) |
| Pin 8 | I/O — Macrocell input/output (bidirectional) |
| Pin 9 | I/O — Macrocell input/output (bidirectional) |
| Pin 10 | I/O — Macrocell input/output (bidirectional) |
| Pin 11 | INPUT — Dedicated input pin |
| Pin 12 | INPUT — Dedicated input pin |
| Pin 13 | GND — Ground reference |
| Pin 14 | INPUT — Dedicated input pin |
| Pin 15 | INPUT — Dedicated input pin |
| Pin 16 | I/O — Macrocell input/output (bidirectional) |
| Pin 17 | I/O — Macrocell input/output (bidirectional) |
| Pin 18 | I/O — Macrocell input/output (bidirectional) |
| Pin 19 | I/O — Macrocell input/output (bidirectional) |
| Pin 20 | I/O — Macrocell input/output (bidirectional) |
| Pin 21 | I/O — Macrocell input/output (bidirectional) |
| Pin 22 | I/O — Macrocell input/output (bidirectional) |
| Pin 23 | I/O — Macrocell input/output (bidirectional) |
| Pin 24 | I/O — Macrocell input/output (bidirectional) |
| Pin 25 | INPUT — Dedicated input pin |
| Pin 26 | INPUT — Dedicated input pin |
| Pin 27 | INPUT — Dedicated input pin |
| Pin 28 | VCC — +5 V supply |
Typical Applications
EP910ILC-12 is suitable for 6 applications: Legacy 5V Glue Logic Replacement, Address Decoding & Bus Arbitration, Industrial Control State Machines, Retro Computing / Vintage Hardware Restoration, Prototype Logic Consolidation, 5V Peripheral Interface Logic.
Legacy 5V Glue Logic Replacement
The EP910ILC-12 directly replaces multiple discrete 74LS244, 74LS245, 74LS138, and 74LS08 SSI/MSI chips on a 5 V logic board, consolidating up to ~450 gates of combinational and registered logic in a single 28-PLCC device. Its 12 ns tPD matches 74LS bipolar logic timing, so address-decoder and bus-buffer circuits drop in without re-timing downstream paths. Non-volatile UV-EPROM storage means instant-on at power-up, with no boot PROM or configuration logic required.
Recommended
Address Decoding & Bus Arbitration
The 24 macrocells and 12 ns tPD of the EP910ILC-12 fit cleanly into 8-bit and 16-bit address-decoding applications in 8086/8088, Z80, 68000, and similar microcontroller or microprocessor systems. It can decode full memory maps, generate chip-select signals, and arbitrate bus requests across multiple peripherals in a single device. The 16 dedicated feedback paths let the macrocells reference each other's outputs, supporting priority-encoded and cascaded decode trees up to 24 deep.
Recommended
Industrial Control State Machines
The industrial temperature grade (-40 °C to +85 °C) of the EP910ILC-12 makes it well-suited for factory-floor state machines driving relays, solenoids, and stepper-motor control logic. Each of the 24 macrocells can implement one state of a finite state machine with combinatorial outputs, and the non-volatile UV-EPROM configuration survives brownouts and noisy power rails without corruption. The 5 V supply tolerance (±5%) tolerates unregulated industrial 24 V-to-5 V DC-DC converter outputs.
Recommended
Retro Computing / Vintage Hardware Restoration
The EP910ILC-12 was a popular glue-logic device in late-1980s and 1990s PC clone motherboards, arcade boards, and vintage industrial controllers. Restoration projects for these systems need pin-compatible replacements to repair board-level faults without re-engineering the surrounding discrete-logic ecosystem. The EP910ILC-12's 28-PLCC J-lead footprint matches the original Altera EP910 sockets, and its 12 ns timing matches the original design margins.
Recommended
Prototype Logic Consolidation
Engineering prototypes that previously needed 8-12 discrete 74HC/74LS logic chips can be consolidated onto a single EP910ILC-12 for faster board spin cycles and easier design revisions. The MAX+PLUS II development environment accepts standard CUPL/ABEL-style HDL or schematic capture, and the 12 ns tPD accommodates most prototype bus-cycle budgets. Once the design stabilizes, the prototype can migrate to a production-grade MAX II or MAX V CPLD if longevity supply is required.
Recommended
5V Peripheral Interface Logic
The EP910ILC-12 can implement custom peripheral interfaces that need to bridge a 5 V microcontroller bus to legacy peripherals with non-standard timing. Common use cases include custom ISA bus decode logic, parallel-port signal conditioning, and proprietary peripheral controllers. The non-volatile EPROM configuration means the interface is ready at power-up, simplifying boot-loader and firmware-update sequencing on the host CPU.
Recommended
Recommended Products Summary
Engineering reference data for EP910ILC-12 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910ILC-15 | EP910IDC-15 | EP910IDI-15 | EP910DC-15 | EP910DC-30 |
|---|---|---|---|---|---|---|
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Package | 28-PLCC (J-Lead) | 28-PLCC (J-Lead) - same | 28-PLCC (J-Lead) - same | 28-PLCC (J-Lead) - same | 28-PLCC (J-Lead) - same | 28-PLCC (J-Lead) - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | 15 ns | 15 ns | 15 ns | 15 ns | 30 ns |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Operating Temperature | -40 °C to +85 °C (industrial) | -40 °C to +85 °C (industrial) | -40 °C to +85 °C (industrial) | -40 °C to +85 °C (industrial) | 0 °C to +70 °C (commercial) | 0 °C to +70 °C (commercial) |
| Memory Technology | UV-EPROM (non-volatile) | UV-EPROM (non-volatile) | UV-EPROM (non-volatile) | UV-EPROM (non-volatile) | UV-EPROM (non-volatile) | UV-EPROM (non-volatile) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Faster speed grade than most EP910 variants (vs EP910ILC-15)
- Industrial temperature grade for harsh environments (vs EP910DC-15)
- Non-volatile EPROM configuration for instant-on behavior (vs Modern SRAM-based FPGAs)
Design Notes
The 28-pin PLCC J-lead package has a JEDEC-standard footprint (0.050 inch pitch, JEDEC MS-018). Use a PLCC-28 socket for prototyping so the chip can be removed for UV erasure and reprogramming - the EP910 Classic EPLD requires a UV windowed ceramic package variant for erasure, but the plastic J-lead 'C' package used here is one-time-programmable (OTP) through standard Altera programming hardware. A PLCC extraction tool is recommended for field upgrades.
Decouple VCC (pin 28) and GND (pin 13) with a 0.1 µF ceramic capacitor placed within 5 mm of the package. The EP910ILC-12 draws a small quiescent current during operation but generates switching transients on every macrocell output transition; a bulk 10 µF tantalum or aluminum electrolytic capacitor at the board supply rail is also recommended for 5 V designs with multiple EPLD/CPLD devices sharing the same rail.
Do not exceed 5.25 V VCC - the UV-EPROM cells can be corrupted at higher voltages during programming or operation. The 'I' suffix in EP910ILC-12 indicates industrial temperature grade; commercial-grade variants (EP910LC-XX, EP910DC-XX) are NOT direct substitutes in designs that must operate below 0 °C or above +70 °C. Verify programming voltage and timing against the EP910 family datasheet, as the 12 ns speed grade has tighter timing margins than the slower 15 ns or 35 ns variants.
The 12 ns tPD is the maximum pin-to-pin delay; actual delay depends on the number of product terms in the macrocell logic equation. Designs using long AND/OR chains should reserve a timing margin of at least 20% below the 12 ns tPD figure to avoid setup-time violations in synchronous logic. For clocked designs, route the clock signal on a dedicated input pin (pins 11, 12, 14, 15, 25, 26, or 27) and avoid using macrocell feedback as a clock source.
Compliance Information
Compliance information was not present in the verified web data. The EP910 family predates widespread RoHS adoption - many EP910ILC-12 lots are non-RoHS by default, but lead-free re-flow compatible variants may exist. Designers requiring RoHS-compliant material must request certification from the distributor at order placement.
