EP910ILC-12 vs EP910IDI-15 Comparison

Detailed side-by-side comparison of EP910ILC-12 by Intel and EP910IDI-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910ILC-12 EP910IDI-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $12.40 $29.00
Product Type Classic EPLD (Erasable Programmable Logic Device) β€”
Family Altera EP910 Classic EPLD Classic EPLD
Number of Macrocells 24 β€”
Usable Gates 450 (typical) β€”
Propagation Delay (tPD) 12 ns (max) β€”
Supply Voltage (VCC) 4.75 V to 5.25 V β€”
Nominal Supply 5 V β€”
Memory Technology UV-erasable CMOS EPROM β€”
Package 28-PLCC (J-Lead, 11.5 x 11.5 mm) 40-pin CDIP (CerDIP) with quartz window
Mounting Type Surface Mount Through-hole (DIP)
Operating Temperature -40 Β°C to +85 Β°C (industrial grade, 'I' suffix) -40C to +85C (industrial, "I" grade)
Configuration Storage Non-volatile EPROM (instant-on) β€”
Programming Method Altera programming algorithm (serial/parallel master-slave) β€”
MSL Level [DATA_NEEDED: MSL level] β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance of CDIP windowed part]
Number of Pins 28 β€”
Feedback Paths 16 dedicated β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Logic Gates β€” 450 gates
Macrocells β€” 24
Maximum User I/O Pins β€” 36
Pin-to-Pin Propagation Delay (tpd) β€” 15 ns
Maximum Counter Frequency β€” 66.6 MHz
Supply Voltage (Vcc) β€” 5 V
Technology β€” CMOS EPROM
Program/Erase Method β€” UV-erasable windowed CerDIP
Macrocells Configurable As β€” D, T, JK, SR flip-flop, or combinatorial
Development Tool β€” MAX+PLUS II (legacy) / Altera Classic compiler
Programming Hardware β€” Altera Logic Programmer card
Logic Family Compatibility β€” Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages

Datasheets & Resources

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