EP910ILC-12 vs EP910ILC-15N Comparison
Detailed side-by-side comparison of EP910ILC-12 by Intel and EP910ILC-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N ObsoleteSpecification Comparison
| Parameter | EP910ILC-12 | EP910ILC-15N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.40 | $9.85 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Family | Altera EP910 Classic EPLD | Classic |
| Number of Macrocells | 24 | β |
| Usable Gates | 450 (typical) | β |
| Propagation Delay (tPD) | 12 ns (max) | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Nominal Supply | 5 V | β |
| Memory Technology | UV-erasable CMOS EPROM | β |
| Package | 28-PLCC (J-Lead, 11.5 x 11.5 mm) | PLCC-44 (J-lead, surface mount) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40 Β°C to +85 Β°C (industrial grade, 'I' suffix) | 0 C to +70 C (commercial) |
| Configuration Storage | Non-volatile EPROM (instant-on) | β |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant |
| Number of Pins | 28 | β |
| Feedback Paths | 16 dedicated | β |
| Logic Gates | β | 450 |
| Macro Cells | β | 24 |
| Maximum Propagation Delay (tPD) | β | 15 ns |
| Maximum Operating Frequency | β | 66.6 MHz |
| User I/O Pins | β | 36 |
| Dedicated Input Pins | β | 16 |
| Process Technology | β | CMOS EPROM (one-time programmable) |
| JTAG Support | β | IEEE 1149.1 boundary-scan |
| Programming | β | EPROM / JTAG (Classic EP-series) |