EP910ILC-15N vs EP910DC-15 Comparison
Detailed side-by-side comparison of EP910ILC-15N by Altera and EP910DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
Specification Comparison
| Parameter | EP910ILC-15N | EP910DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $10.75 |
| Family | Classic | Altera Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Logic Gates | 450 | β |
| Macro Cells | 24 | β |
| Maximum Propagation Delay (tPD) | 15 ns | 15 ns |
| Maximum Operating Frequency | 66.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| User I/O Pins | 36 | β |
| Dedicated Input Pins | 16 | β |
| Package | PLCC-44 (J-lead, surface mount) | 24-pin ceramic DIP (DC) |
| Mounting Type | Surface Mount | Through-Hole |
| Operating Temperature | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM (one-time programmable) | β |
| JTAG Support | IEEE 1149.1 boundary-scan | β |
| RoHS Status | Compliant | [DATA_NEEDED: not explicitly stated in verified data] |
| Programming | EPROM / JTAG (Classic EP-series) | β |
| Device Density | β | 900 usable gates |
| Macrocells | β | 24 |
| Logic Elements | β | [DATA_NEEDED: exact LE count] |
| Dedicated Inputs | β | 12 |
| Bidirectional I/O Pins | β | 12 |
| Flip-Flops | β | 10 |
| Product Terms per Macrocells | β | 24 |
| Speed Grade | β | 15 |
| Technology | β | CMOS EPROM, UV-erasable |
| MSL Level | β | [DATA_NEEDED: MSL level] |