EP910ILC-15N vs EP910ILC-25 Comparison
Detailed side-by-side comparison of EP910ILC-15N by Altera and EP910ILC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
Specification Comparison
| Parameter | EP910ILC-15N | EP910ILC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $9.95 |
| Family | Classic | EP910 Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Logic Gates | 450 | β |
| Macro Cells | 24 | β |
| Maximum Propagation Delay (tPD) | 15 ns | β |
| Maximum Operating Frequency | 66.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | β |
| User I/O Pins | 36 | 36 |
| Dedicated Input Pins | 16 | β |
| Package | PLCC-44 (J-lead, surface mount) | 44-pin JLCC (windowed ceramic) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Process Technology | CMOS EPROM (one-time programmable) | β |
| JTAG Support | IEEE 1149.1 boundary-scan | β |
| RoHS Status | Compliant | non_compliant (ceramic windowed package) |
| Programming | EPROM / JTAG (Classic EP-series) | β |
| Macrocells | β | 24 |
| Propagation Delay (tPD) | β | 25 ns |
| Internal Frequency (fMAX) | β | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | β | Sum-of-products AND/OR array |
| Technology | β | CMOS EPROM (UV-erasable) |
| Configuration Memory | β | Non-volatile EPROM (windowed ceramic) |
| Supply Voltage | β | 5 V |
| Development Tool | β | Altera MAX+PLUS II (legacy) |
| Lifecycle Status | β | Obsolete - last time buy was late 1990s |