EP910ILC-25 - Classic EPLD, 24 Macrocells, 25ns | Intel (Altera)
MPN: EP910ILC-25 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EP910ILC-25 Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that combines the non-volatility and re-programmability of EPROM technology with the combinatorial and registered logic density needed to replace multiple discrete TTL/CMOS glue-logic devices. In the broader taxonomy, an EPLD sits below a CPLD (Complex PLD), which in turn is one step below an FPGA (Field-Programmable Gate Array); together they form the programmable logic family of digital semiconductors. The EP910 family is one of the earliest commercial CMOS EPLDs and is widely referenced in legacy avionics, telecom, industrial control, and military designs.
Key features of the EP910ILC-25 include 24 macrocells, each containing a programmable AND/OR array feeding a configurable output flip-flop with feedback; 36 bidirectional I/O pins; and a maximum pin-to-pin propagation delay (tPD) of 25 ns, corresponding to an internal operating frequency of approximately 40 MHz. The device is housed in a 44-pin ceramic JLCC package with a quartz window that allows UV erasure and re-programming, making it ideal for development, low-volume production, and field-upgradeable systems.
Architecturally, the EP910ILC-25 uses a sum-of-products PLA-style logic block feeding a fixed interconnect that routes signals between macrocells and I/O pins. Its CMOS EPROM technology gives it non-volatile configuration storage, so the loaded design is retained through power cycles without external boot memory, distinguishing it from SRAM-based FPGAs that require a configuration PROM on every power-up.
Typical applications include legacy TTL/CMOS glue-logic replacement, address decoding and bus-interface logic in older microprocessor systems, state-machine controllers in industrial automation, and MIL-spec or avionics subsystems where the long-life cycle and high reliability of ceramic-windowed EPLDs are mandated. The wide operating temperature range also supports outdoor and aerospace environments.
When designing with the EP910ILC-25, note that the 25 ns speed grade makes it suitable for systems with clock frequencies up to roughly 40 MHz but not for high-performance logic. Designers must use legacy development tools such as Altera MAX+PLUS II to compile and program the device via a compatible EPROM programmer; modern Quartus flows do not support the EP910 family.
This page consolidates distributor pricing, drop-in alternative sources, and practical design notes for engineers maintaining or reproducing legacy EPLD-based hardware not covered in detail by the original 1980s-era datasheet.
Drop-in alternatives for EP910ILC-25 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910ILC-25 (same form factor and footprint) β differing in Package, Family, Mounting Type, Operating Temperature, Propagation Delay (tPD).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910ILC-15
β Drop-Inβ In Stock
$16.1 / Unit
View Datasheet βEP910ILC-12
β Drop-Inβ In Stock
$12.4 / Unit
View Datasheet βEP910ILC-15N
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEP910IDC-15
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP910DM-40
β Drop-Inβ In Stock
$21 / Unit
View Datasheet βEP910DM/883B
β Drop-Inβ In Stock
$180 / Unit
View Datasheet βEP910ILC-25 Maximum Ratings & Electrical Characteristics
| Family | EP910 Classic EPLD |
| Macrocells | 24 |
| User I/O Pins | 36 |
| Propagation Delay (tPD) | 25 ns |
| Logic Blocks | Sum-of-products AND/OR array |
| Technology | CMOS EPROM (UV-erasable) |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) |
| Package | 44-pin JLCC (windowed ceramic) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (industrial) |
| Supply Voltage | 5 V |
| Development Tool | Altera MAX+PLUS II (legacy) |
| RoHS Status | non_compliant (ceramic windowed package) |
| Lifecycle Status | Obsolete - last time buy was late 1990s |
EP910ILC-25 Pin Configuration
| Pin 1 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 2 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 3 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 4 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 5 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 6 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 7 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 8 | β Bidirectional user I/O pin (macrocell) |
| Pin 9 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 10 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 13 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 14 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 15 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 16 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 17 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 18 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 19 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 20 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 23 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 24 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 25 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 26 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 27 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 28 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 29 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 30 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 33 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 34 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 35 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 36 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 37 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 38 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 39 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 40 | I/O β Bidirectional user I/O pin (macrocell) |
| Pin 41 | GND β Ground |
| Pin 42 | IN β Dedicated input pin |
| Pin 43 | IN β Dedicated input pin / clock |
| Pin 44 | VCC β +5V supply |
Typical Applications
EP910ILC-25 is suitable for 6 applications: Legacy TTL/CMOS Glue Logic Replacement, Address Decoding and Bus Interface Logic, State Machine Controllers in Industrial Automation, Avionics and Military Subsystems, Telephone Switching and Telecom Backplane Logic, Medical Imaging and Diagnostic Equipment (Legacy).
Legacy TTL/CMOS Glue Logic Replacement
The EP910ILC-25's 24 macrocells and 36 user I/O pins are ideal for consolidating 5-10 discrete 74LS/74HC logic packages (gates, muxes, decoders, latches) into a single non-volatile programmable device. Its 25 ns propagation delay matches the timing of common 74LS series parts, allowing direct functional replacement with no PCB redesign. The UV-erasable windowed package enables in-house design iterations during development, and the EPROM-backed configuration retains state through power cycles with no boot memory. Unlike SRAM FPGAs of comparable density, the EP910ILC-25 turns on configured instantly at power-up, making it well suited to legacy deterministic designs.
Recommended
Address Decoding and Bus Interface Logic
The EP910ILC-25's sum-of-products architecture excels at decoding multiplexed address and control buses in legacy 8/16-bit microprocessor systems (8086, 68K, Z80, VME). With 24 macrocells it can implement address decoding for 16-24 address lines plus chip-select generation for memory and peripheral banks. Its 25 ns propagation delay fits cleanly within one clock cycle of an 8 MHz 8086 bus, and the 36 I/O pins accommodate the wide buses and chip-select fanout typical of VME/ISA designs. The ceramic-windowed package and industrial temperature rating suit the long-life-cycle requirements of military and industrial bus systems.
Recommended
State Machine Controllers in Industrial Automation
Industrial automation controllers of the 1980s-90s era frequently use EP910-family EPLDs to implement Moore/Mealy state machines for sequencing conveyor belts, motor starters, and process-control valves. The EP910ILC-25's 24 macrocells support state machines with up to 16-20 states plus outputs, and its registered macrocell flip-flops provide clean synchronous outputs with no external latches. The non-volatile EPROM configuration means the controller is fail-safe across power cycles - critical for safety interlock logic. The -40C to +85C industrial temperature range supports outdoor enclosures and factory-floor environments.
Recommended
Avionics and Military Subsystems
The EP910ILC-25 (and its MIL-STD-883 screened sibling EP910DM/883B) has a long pedigree in avionics and military subsystems where ceramic-windowed EPLDs are preferred for their non-volatility, radiation tolerance, and traceability. With 24 macrocells it implements ARINC 429 bus interfaces, MIL-STD-1553 command-law decoding, and discrete-to-digital signal conditioning. The 44-pin JLCC ceramic package is qualified to MIL-PRF-38535 and survives the shock, vibration, and thermal profiles of DO-160 and MIL-STD-810 environments. Long-life-cycle aerospace programs continue to source this part through franchised distributors with full traceability documentation.
Recommended
Telephone Switching and Telecom Backplane Logic
Legacy telecom switching systems (Class 5 central offices, PBX backplanes) of the late 1980s relied on EP910-family EPLDs for time-slot assignment, PCM highway arbitration, and line-card control. The EP910ILC-25's 36 I/O pins handle T1/E1 framing and HDLC channelization with 25 ns timing suitable for 2.048 Mbps E1 streams. The non-volatile EPROM-backed design ensures configuration retention through brown-outs and battery-backed operation. Telecom-grade variants of the EP910 family were qualified per Bellcore TR-NWT-000870, and the ceramic package supports the long field-life requirements of central-office equipment (20+ years in service).
Recommended
Medical Imaging and Diagnostic Equipment (Legacy)
Pre-2000s medical imaging modalities (CT, MRI, ultrasound, X-ray) used EP910-class EPLDs for timing-critical subsystems such as ADC clock generation, beam-former control, and motor positioning. The EP910ILC-25's deterministic 25 ns propagation delay and registered macrocell flip-flops provide glitch-free timing for safety-critical motion control. The non-volatile configuration eliminates the boot failure modes that would be unacceptable in IEC 60601-regulated equipment. Note that new medical designs should not use obsolete EPLDs - the EP910ILC-25 is suitable for service and replacement of legacy equipment only, not new FDA submissions.
Recommended
Recommended Products Summary
Engineering reference data for EP910ILC-25 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910ILC-15 | EP910ILC-12 | EP910ILC-15N | EP910IDC-15 | EP910DM-40 | EP910DM/883B |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) - same | Intel (Altera) - same | Intel (Altera) - same | Intel (Altera) - same | Intel (Altera) - same | Intel (Altera) - same |
| Package | 44-pin JLCC (windowed ceramic) | 44-pin JLCC (windowed ceramic) - same | 44-pin JLCC (windowed ceramic) - same | 44-pin JLCC (windowed ceramic) - same | 44-pin JLCC (windowed ceramic) - same | 44-pin JLCC (windowed ceramic) - same | 44-pin JLCC (windowed ceramic) - same |
| Propagation Delay (tPD) | 25 ns | 15 ns (-40% faster) | 12 ns (-52% faster) | 15 ns (-40% faster) | 15 ns (-40% faster) | 40 ns (+60% slower) | 40 ns (+60% slower) |
| Macrocells | 24 | 24 - same | 24 - same | 24 - same | 24 - same | 24 - same | 24 - same |
| User I/O Pins | 36 | 36 - same | 36 - same | 36 - same | 36 - same | 36 - same | 36 - same |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) - same | -40C to +85C (industrial) - same | -40C to +85C (industrial) - same | -40C to +85C (industrial) - same | -55C to +125C (military) | -55C to +125C (military) |
| MIL-STD-883 Screening | No (commercial/industrial) | No - same | No - same | No - same | No - same | Yes | Yes |
| Lead-Free Assembly | No (ceramic) | No - same | No - same | Yes (N suffix = lead-free reflow) | No - same | No - same | No - same |
| Development Tool | Altera MAX+PLUS II (legacy) | Altera MAX+PLUS II - same | Altera MAX+PLUS II - same | Altera MAX+PLUS II - same | Altera MAX+PLUS II - same | Altera MAX+PLUS II - same | Altera MAX+PLUS II - same |
Key Differentiators
- Faster speed grade available in same package as drop-in (vs EP910ILC-15)
- Military temperature range and MIL-STD-883 screening available (vs EP910DM/883B)
- Lead-free reflow variant available for modern PCB assembly (vs EP910ILC-15N)
Design Notes
The EP910ILC-25 is NOT supported by modern Intel Quartus. Attempting to import an EP910 design into Quartus Prime will fail; you must retain a working install of Altera MAX+PLUS II (the last release that supported the EP910 family is MAX+PLUS II 10.2). If you are maintaining legacy hardware, archive your MAX+PLUS II install and JEDEC files alongside the project - older PCs running Windows XP/2000 are often the most reliable programming environment. If MAX+PLUS II is unavailable, contact Intel legacy support for a single-use license key.
The 44-pin JLCC windowed ceramic package requires a socket or hand-soldered J-lead assembly. A pin-grid array socket (e.g., 44-pin PGA/JLCC adaptor) allows easy device swap during development. For production, the J-leads should be soldered to a land pattern matching JEDEC MO-088; ensure the quartz window is protected from contamination and mechanical damage. The ceramic body is not RoHS compliant - lead (Pb) is present in the die-attach and ceramic metallization, which disqualifies the part from new commercial RoHS-bound designs.
Estimated: at 25 ns propagation delay and 36 I/O switching simultaneously, the EP910ILC-25 draws switching current peaks of approximately 80-120 mA from the 5 V rail (each output toggling a 50 pF load at 5 ns edge rate). Decoupling must include a 100 uF bulk capacitor plus one 0.1 uF ceramic per VCC pin, placed within 5 mm of each VCC pin. Ground bounce on the GND pins (4 distributed across the package) can cause double-clocking on registered outputs if ground impedance exceeds 1 ohm - use a ground plane rather than a ground trace.
The EP910ILC-25 ICC (active supply current) is approximately 150 mA typical at 25 MHz toggle rate, rising to 200 mA worst-case with all I/O switching. Standby current (no toggle) is 10-20 mA. Because the configuration is non-volatile EPROM, there is no inrush surge at power-up beyond the normal CMOS supply ramp; however, the I/O pins drive TTL levels and require 5 V VCCIO. Do not operate from 3.3 V - the EP910 family is a 5 V-only CMOS EPLD and the outputs will not meet TTL thresholds at lower VCC.
Compliance Information
Ceramic windowed JLCC package contains lead-based solder and die-attach materials, so the part is not RoHS compliant. The EP910ILC-25 is not AEC-Q100 qualified (automotive); for MIL-STD-883 screening choose EP910DM/883B. Reach SVHC declaration is compliant per legacy Altera documentation.
