EP910ILC-15N vs EP910ILC-50 Comparison
Detailed side-by-side comparison of EP910ILC-15N by Altera and EP910ILC-50 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N ObsoleteSpecification Comparison
| Parameter | EP910ILC-15N | EP910ILC-50 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $10.85 |
| Family | Classic | Altera Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Logic Gates | 450 | β |
| Macro Cells | 24 | β |
| Maximum Propagation Delay (tPD) | 15 ns | β |
| Maximum Operating Frequency | 66.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| User I/O Pins | 36 | 24 |
| Dedicated Input Pins | 16 | 12 |
| Package | PLCC-44 (J-lead, surface mount) | PLCC-44 (J-lead) |
| Mounting Type | Surface Mount | Surface Mount (socket-compatible) |
| Operating Temperature | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM (one-time programmable) | β |
| JTAG Support | IEEE 1149.1 boundary-scan | β |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Programming | EPROM / JTAG (Classic EP-series) | β |
| Macrocells | β | 24 |
| Usable Gates | β | 900 (typical) |
| Maximum Frequency | β | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | β | 50 ns |
| Technology | β | CMOS EPROM, UV-erasable |
| Programming Cycles | β | 100 (minimum) |
| Boundary Scan | β | IEEE 1149.1 JTAG (selected speed grades) |