EP910ILC-50 - Classic EPLD, 900 Gates, 50ns PLCC-44 | Intel
MPN: EP910ILC-50 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.85 | $10,850.00 |
EP910ILC-50 Overview
A Classic EPLD is a UV-erasable, electrically programmable logic device that sits in the hierarchy between discrete PAL/GAL and modern SRAM-based CPLDs/FPGAs. Programmable AND/OR macrocell architecture combines PAL-like speed with sum-of-products flexibility, while non-volatile EPROM cells retain configuration without external boot memory. Compared with contemporary SRAM FPGAs, Classic EPLDs offer instant-on behavior, deterministic timing, and excellent design security.
Key features of the EP910ILC-50 include 24 macrocells, 12 dedicated input pins, 24 I/O pins arranged in four LAB-style groups, a 50 ns tpd commercial timing specification, and a 5V VCC supply typical of the Classic family. The device is housed in a J-leaded PLCC-44 surface-mount package suitable for socketed programming and field upgrades. Macrocells include configurable flip-flop polarity, output enable control, and product-term sharing for efficient state-machine implementation.
The EP910 is implemented in 0.8 um-class CMOS EPROM process technology with a 5V programming algorithm and supports up to 100 erase/program cycles. Built-in JTAG (IEEE 1149.1) boundary-scan test logic on selected speed grades simplifies board-level test, and the device is supported by the Altera MAX+PLUS II development environment (legacy). The Classic architecture delivers predictable timing across commercial and industrial temperature ranges, making it well suited for replacement and maintenance of legacy designs.
Typical applications include address decoding and bus interfacing in 5V microprocessor systems, peripheral glue logic in industrial controllers, state-machine controllers in instrumentation, and legacy telecom/military replacement programs where the original Altera Classic design must be replicated. The instant-on non-volatile configuration makes the EP910ILC-50 attractive for safety-critical and security-sensitive designs that cannot tolerate FPGA configuration latency.
When designing with this part, note that the Classic family is in legacy/last-time-buy status with most speed grades and is increasingly hard to source. Engineers maintaining existing EP910 designs should qualify the EP910ILC-50 or a pin-compatible Classic variant, and consider migrating to MAX 7000-series CPLDs for new designs.
This page synthesizes distributor pricing, datasheet-cited parameters, pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP910ILC-50 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910ILC-50 (same form factor and footprint) — differing in Package, Family, Propagation Delay (tPD), Mounting Type, Programming Method.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910ILC-12
✅ Drop-In✓ In Stock
$12.4 / Unit
View Datasheet →EP910ILC-15
✅ Drop-In✓ In Stock
$16.1 / Unit
View Datasheet →EP910ILC-15N
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EP910ILC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP900ILC-50
✅ Drop-In📋 Reference alternative (not in catalog)
EP910ILC-50 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Macrocells | 24 |
| Usable Gates | 900 (typical) |
| Pin-to-Pin Delay (tpd) | 50 ns |
| Supply Voltage (VCC) | 5 V (typical) |
| User I/O Pins | 24 |
| Dedicated Input Pins | 12 |
| Package | PLCC-44 (J-lead) |
| Mounting Type | Surface Mount (socket-compatible) |
| Technology | CMOS EPROM, UV-erasable |
| Operating Temperature | 0C to +70C (commercial) |
| Programming Cycles | 100 (minimum) |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) |
EP910ILC-50 Pin Configuration
| Pin 1 | I/O — Bidirectional user I/O pin (group 1) |
| Pin 2 | I/O — Bidirectional user I/O pin (group 1) |
| Pin 3 | I/O — Bidirectional user I/O pin (group 1) |
| Pin 4 | I/O — Bidirectional user I/O pin (group 1) |
| Pin 5 | I/O — Bidirectional user I/O pin (group 1) |
| Pin 6 | I/O — Bidirectional user I/O pin (group 1) |
| Pin 7 | I/O — Bidirectional user I/O pin (group 1) |
| Pin 8 | I/O — Bidirectional user I/O pin (group 1) |
| Pin 9 | I/O — Bidirectional user I/O pin (group 1) |
| Pin 10 | I/O — Bidirectional user I/O pin (group 1) |
| Pin 11 | GND — Ground |
| Pin 12 | INPUT — Dedicated input pin |
| Pin 13 | INPUT — Dedicated input pin |
| Pin 14 | INPUT — Dedicated input pin |
| Pin 15 | INPUT — Dedicated input pin |
| Pin 16 | INPUT — Dedicated input pin |
| Pin 17 | INPUT — Dedicated input pin |
| Pin 18 | INPUT — Dedicated input pin |
| Pin 19 | INPUT — Dedicated input pin |
| Pin 20 | INPUT — Dedicated input pin |
| Pin 21 | INPUT — Dedicated input pin |
| Pin 22 | INPUT — Dedicated input pin |
| Pin 23 | INPUT — Dedicated input pin / clock |
| Pin 24 | VCC — +5V power supply |
| Pin 25 | I/O — Bidirectional user I/O pin (group 2) |
| Pin 26 | I/O — Bidirectional user I/O pin (group 2) |
| Pin 27 | I/O — Bidirectional user I/O pin (group 2) |
| Pin 28 | I/O — Bidirectional user I/O pin (group 2) |
| Pin 29 | I/O — Bidirectional user I/O pin (group 2) |
| Pin 30 | I/O — Bidirectional user I/O pin (group 2) |
| Pin 31 | I/O — Bidirectional user I/O pin (group 2) |
| Pin 32 | I/O — Bidirectional user I/O pin (group 2) |
| Pin 33 | I/O — Bidirectional user I/O pin (group 2) |
| Pin 34 | I/O — Bidirectional user I/O pin (group 2) |
| Pin 35 | GND — Ground |
| Pin 36 | I/O — Bidirectional user I/O pin (group 3) |
| Pin 37 | I/O — Bidirectional user I/O pin (group 3) |
| Pin 38 | I/O — Bidirectional user I/O pin (group 3) |
| Pin 39 | I/O — Bidirectional user I/O pin (group 3) |
| Pin 40 | I/O — Bidirectional user I/O pin (group 3) |
| Pin 41 | I/O — Bidirectional user I/O pin (group 3) |
| Pin 42 | I/O — Bidirectional user I/O pin (group 3) |
| Pin 43 | I/O — Bidirectional user I/O pin (group 3) |
| Pin 44 | I/O — Bidirectional user I/O pin (group 3) |
Typical Applications
EP910ILC-50 is suitable for 7 applications: 5V Microprocessor Address Decoding, Industrial Glue Logic Replacement, State Machine Controllers in Instrumentation, Legacy Telecom Interface Logic, Military/Aerospace Legacy Avionics, Educational and Development Platforms, Retrocomputing and Vintage Hardware Restoration.
5V Microprocessor Address Decoding
The EP910ILC-50's 24 macrocells and 50 ns tpd make it a strong fit for 5V microprocessor address decoding and bus interfacing, where the device sits between the CPU and peripheral devices to generate chip-select signals. With 12 dedicated inputs and 24 user I/O pins, it can decode wide address buses (16-24 bit) and produce multiple bank-select outputs simultaneously. Compared to discrete 74LS-series decoder logic, the EP910ILC-50 replaces 4-8 SSI/MSI packages in a single PLCC-44 footprint, reducing board area by 60-70% and improving design flexibility via in-system reprogramming (UV erase required). Engineers should reserve one or two macrocells for active-low chip-select polarity and use the global clock network for synchronous handshaking where needed.
Recommended
Industrial Glue Logic Replacement
The EP910ILC-50 is widely used in legacy industrial controllers where it consolidates discrete 74HC/74LS glue logic - bus transceivers, latches, parity generators, and interrupt controllers - into a single programmable device. Its 5V VCC and CMOS EPROM technology match the supply rails of older industrial PLCs and motor controllers without level shifting. The 50 ns tpd is more than adequate for sub-10 MHz control loops typical of PLC scan times (1-10 ms). The instant-on non-volatile EPROM configuration eliminates the boot delay of SRAM FPGAs, ensuring deterministic power-on behavior critical in safety-instrumented systems. Engineers maintaining Allen-Bradley, Siemens, or ABB legacy I/O modules rely on the EP910ILC-50 for field repair.
Recommended
State Machine Controllers in Instrumentation
The EP910ILC-50 supports medium-complexity state machines found in test and measurement instruments, including sequencers, protocol converters, and waveform generators. Each macrocell provides a configurable D/T/JK flip-flop with polarity control, allowing 24-state FSMs without external state registers. The 900-gate equivalent capacity accommodates 50-100 state transitions typical of IEEE-488 (GPIB) handlers, RS-232 protocol engines, or scanner controllers. The 50 ns tpd enables state transitions at up to 20 MHz clock rates, sufficient for most serial protocol bit-rate generation. Compared to microcontrollers, the EP910ILC-50 offers deterministic interrupt-free timing that simplifies EMI compliance in sensitive analog instruments.
Recommended
Legacy Telecom Interface Logic
The EP910ILC-50 historically served in telecom equipment for T1/E1 framer interfacing, channel-associated signaling, and time-slot assignment logic. The 24-macrocell / 24-I/O structure aligns well with 8-bit parallel telephony buses plus framing overhead. The 5V supply matches legacy telecom backplanes, eliminating the need for level translation that modern 3.3V CPLDs would require. The non-volatile EPROM configuration is valued in central-office equipment where SRAM FPGA bitstream corruption from soft errors is unacceptable. Maintenance programs for Lucent 5ESS, Nortel DMS, and Alcatel-Lucent legacy switch line cards continue to source the EP910ILC-50 through broker channels.
Recommended
Military/Aerospace Legacy Avionics
The EP910 family includes MIL-STD-883B-processed variants (EP910DM/883B, EP910DM-40) suited for legacy avionics and military platforms where the design is locked but components must be sourced for decades of field support. The EP910ILC-50 commercial variant serves as a development and qualification proxy for these military parts, with identical macrocell architecture and pinout in PLCC-44. The deterministic CMOS EPROM behavior and predictable timing simplify DO-254 design assurance for safety-critical flight controls. Sourced through QPL/QML distributors with full traceability, the EP910DM/883B variant supports long-term sustainment of F-16, AH-64, and C-130 avionics upgrades through 2030+.
Recommended
Educational and Development Platforms
The EP910ILC-50 is used in university digital-logic and computer-architecture labs where students learn programmable logic fundamentals on a non-volatile platform that does not require SRAM bitstream loading. The 50 ns tpd provides clear, observable propagation delays in oscilloscope labs, helping students grasp timing analysis without GHz-speed FPGA complexity. The PLCC-44 socket allows UV erase and reprogramming of the same physical part across multiple lab sessions, reducing per-student cost. The MAX+PLUS II legacy toolchain, though discontinued, remains freely available for educational use and teaches fundamental concepts like product-term allocation, macrocell fitting, and JTAG boundary-scan.
Recommended
Retrocomputing and Vintage Hardware Restoration
The EP910ILC-50 is sought by retrocomputing enthusiasts restoring vintage Sun Microsystems workstations, NeXT computers, and early-1990s arcade boards that used Altera Classic EPLDs for video timing, DMA control, or bus arbitration. The 5V supply, PLCC-44 footprint, and 50 ns tpd match the original design specifications exactly, allowing authentic repairs without FPGA-based modernizations that would alter system behavior. EPROM retention over 30+ years has been generally good for properly stored parts, though UV window covers must remain opaque to preserve data. Hobbyists share programming files (JEDEC) in online archives such as bitsavers.org, enabling faithful restoration of vintage logic designs.
Recommended
Recommended Products Summary
Engineering reference data for EP910ILC-50 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910ILC-12 | EP910ILC-15 | EP910ILC-15N | EP910ILC-25 | EP900ILC-50 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PLCC-44 | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) |
| Pin-to-Pin Delay (tpd) | 50 ns | 12 ns | 15 ns | 15 ns | 25 ns | 50 ns |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 (EP900 family, -50% usable gates) |
| Usable Gates | 900 | 900 | 900 | 900 | 900 | 450 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | Industrial grade | 0C to +70C | 0C to +70C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Pin-compatible faster speed grades available for timing upgrades (vs EP910ILC-25)
- Reduced-density drop-in option for cost-sensitive designs (vs EP900ILC-50)
- Industrial temperature variant in same package (vs EP910ILC-15N)
Design Notes
The EP910ILC-50 is in obsolete lifecycle status as of 2026-09-10; sourcing for new production should include safety stock or a qualified pin-compatible replacement plan. Counterfeit risk is elevated in the secondary market - verify Altera/Intel date codes, lot traceability, and UV-window integrity (opaque label) before committing to high-volume orders. Distributors like Jotrin and Nantian offer authentication certificates on request.
Estimated: The EP910ILC-50 draws approximately 100-150 mA typical ICC at 5V in active operation (per Classic family datasheet convention), giving ~0.5-0.75 W dissipation. PLCC-44 has a typical theta_JA of ~50 C/W, so junction temperature rise is ~25-40 C above ambient at full activity - acceptable for commercial 0-70C operation. Add 100 nF decoupling near each VCC pin (pins 24 and 35 are GND; VCC is on pin 24 in PLCC-44) and bulk 10 uF at board entry. UV-erase window programming requires 12.5V VPP and specific timing - use a validated programmer (e.g., Data I/O, BP Microsystems) supporting Classic EPLDs.
The PLCC-44 socket (e.g., 3M Textool or Aries low-profile) is strongly recommended for development to allow UV-erase and reprogramming cycles. For production, the device can be hand-soldered with hot-air rework or reflowed in a standard SMT profile (peak 225-235 C for 60 seconds, per Altera Classic guidelines). Keep high-speed traces short and match impedance to minimize reflections on clock and global OE lines; place a 33 ohm series resistor on the global clock if ringing exceeds 10% of VCC at the destination flip-flop.
Assign JTAG pins (TDI, TDO, TMS, TCK) to dedicated input pins or user I/O according to the EP910 datasheet IEEE 1149.1 specification for selected speed grades - not all EP910 variants support JTAG. Reserve one macrocell as a JTAG flag for board-level test visibility. Decouple each VCC pin with 0.1 uF X7R ceramic placed within 5 mm of the package; add a 10 uF tantalum or ceramic bulk capacitor at board entry. Connect all GND pins (multiple) to a low-impedance ground plane to minimize ground bounce during simultaneous switching outputs (SSO).
Compliance Information
RoHS/REACH compliance not confirmed in verified web data. EP910 Classic family predates RoHS; commercial variants may use SnPb finish. Lead-free and halogen-free status unknown - verify with distributor or request manufacturer compliance certificate. For military/aerospace use, the EP910DM/883B variant is the qualified MIL-STD-883B option.
