EP910IPC-15 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910IPC-15 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-15 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $15.60 |
| Device Family | Altera Classic EPLD (EP910 series) | β |
| Product Type | Erasable Programmable Logic Device (EPLD) | β |
| Architecture | PAL-type, CMOS | PAL-type AND-OR sum-of-products, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| I/O Pins | 24 | β |
| Product Terms | 240 | β |
| External Clocks | 2 | β |
| Propagation Delay (tPD) | 15 ns | 30 ns (max) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Operating Temperature | 0C to +70C (commercial, IPC suffix) | 0C to +70C (commercial) |
| Package | PDIP-40 (Plastic DIP, 40-pin) | DIP-40 (through-hole, 600 mil) |
| Mounting Type | Through-Hole | Through-Hole |
| Process Technology | CMOS | CMOS |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | UV-Erasable / OTP |
| Pin Count | 40 | β |
| RoHS Status | [DATA_NEEDED: rohs status not confirmed in verified data] | β |
| Family | β | Classic EPLD (EP910 series) |
| Gate Count | β | 900 usable gates |
| Clock Frequency (fCNT) | β | 33.3 MHz |
| Outputs (Macrocells) | β | 24 |
| External Clock Pins | β | 2 (CLK1, CLK2) |
| Supply Voltage | β | 5 V |