EP910IPC-15 vs EP910IDC-15 Comparison
Detailed side-by-side comparison of EP910IPC-15 by Altera and EP910IDC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-15 | EP910IDC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $9.95 |
| Device Family | Altera Classic EPLD (EP910 series) | β |
| Product Type | Erasable Programmable Logic Device (EPLD) | β |
| Architecture | PAL-type, CMOS | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 10 |
| I/O Pins | 24 | 24 |
| Product Terms | 240 | β |
| External Clocks | 2 | β |
| Propagation Delay (tPD) | 15 ns | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Operating Temperature | 0C to +70C (commercial, IPC suffix) | β |
| Package | PDIP-40 (Plastic DIP, 40-pin) | 40-pin CDIP (Ceramic DIP, through-hole) |
| Mounting Type | Through-Hole | β |
| Process Technology | CMOS | β |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | β |
| Pin Count | 40 | β |
| RoHS Status | [DATA_NEEDED: rohs status not confirmed in verified data] | non_compliant (ceramic DIP contains lead) |
| Manufacturer | β | Altera (now Intel PSG) |
| Family | β | Classic EPLD |
| Equivalent Gates | β | 450 |
| Flip-Flops | β | 48 |
| Pin-to-Pin Delay (tPD) | β | 15 ns |
| Maximum Frequency (fCNT) | β | 66.6 MHz |
| Terminal Count | β | 40 |
| Terminal Form | β | Through-Hole |
| Temperature Grade | β | Commercial (0C to +70C) |
| Programmable Security Bit | β | Yes |
| On-board Test Circuitry | β | Yes |
| Logic Type | β | UV Erasable EPROM-based |
| Programming Technology | β | EPROM (UV-erasable) |