EP910IPC-15 vs EP910IPC-50 Comparison
Detailed side-by-side comparison of EP910IPC-15 by Altera and EP910IPC-50 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-15 | EP910IPC-50 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $13.85 |
| Device Family | Altera Classic EPLD (EP910 series) | β |
| Product Type | Erasable Programmable Logic Device (EPLD) | Erasable Programmable Logic Device (EPLD) |
| Architecture | PAL-type, CMOS | β |
| Macrocells | 24 | β |
| Dedicated Inputs | 12 | β |
| I/O Pins | 24 | β |
| Product Terms | 240 | β |
| External Clocks | 2 | β |
| Propagation Delay (tPD) | 15 ns | 50 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0C to +70C (commercial, IPC suffix) | -40C to +85C (industrial) |
| Package | PDIP-40 (Plastic DIP, 40-pin) | 40-pin Ceramic DIP (IPC, windowed) |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS | β |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | Off-board EPROM programmer + UV erase |
| Pin Count | 40 | β |
| RoHS Status | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: not stated in verified data] |
| Family | β | Altera Classic EPLD |
| Logic Capacity | β | [DATA_NEEDED: macrocell count / equivalent gates] |
| Clock-to-Output (tCO) | β | 35 ns |
| Maximum Toggle Frequency | β | [DATA_NEEDED: fMAX] |
| User I/O Pins | β | 24 |
| Technology | β | CMOS EPROM cell |
| Erasure Method | β | UV light through ceramic window (IPC package) |