EP910IPC-50 - Altera Classic EPLD, 50ns, 24 I/O, DIP-40 | Altera
MPN: EP910IPC-50 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.75 | $247.50 |
| 100 | $19.4 | $1,940.00 |
| 500 | $16.2 | $8,100.00 |
| 1,000 | $13.85 | $13,850.00 |
EP910IPC-50 Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines AND/OR arrays with output macrocells, sitting in the historical taxonomy between PALs and modern CPLDs. EPLDs use UV-erasable EPROM cells to retain configuration, and they belong to the broader family of programmable logic devices that today includes CPLDs and FPGAs. As a Classic-series part, the EP910IPC-50 represents an early generation of CMOS programmable logic, optimised for low static power consumption and predictable, deterministic pin-to-pin timing.
Key features of the EP910IPC-50 include 24 available I/O pins, a maximum propagation delay of 50ns (with tCO of 35ns), an internal flip-flop toggle frequency around 26 MHz, and 5V (4.75V to 5.25V) single-supply operation. The device is housed in a 40-pin ceramic DIP (windowed) package for UV erasure and reprogramming, and is specified over an industrial temperature range of -40C to +85C. Output drive current is sufficient for standard TTL/CMOS loads, and the architecture supports combinatorial and registered logic with separate configurable output macrocells.
The EP910 uses a sum-of-products architecture with 72 product terms distributed across its macrocells, allowing designers to replace multiple discrete SSI/MSI logic packages with a single EPLD. The device is programmed using a standard EPROM programmer and erased via UV exposure through the ceramic window, which is the defining characteristic of the IPC (Industrial Pin-grid Ceramic) windowed package. The Classic EPLD family was popular for glue logic, bus decoding, and state-machine applications in the 1980s and early 1990s.
Typical applications for the EP910IPC-50 include bus interface and address decoding in legacy microprocessor systems, replacement of discrete TTL/CMOS glue logic, state-machine and sequencer logic in industrial controllers, and prototyping of custom registered logic. It is also commonly used in educational settings where UV-erasable windowed packages are advantageous for repeated lab cycles.
When designing with the EP910IPC-50, ensure that all unused I/O pins are configured correctly per the datasheet, and verify that the timing model (tPD, tCO, tSU) meets the target system clock budget. Because the part uses EPROM cells, the device is not in-system programmable and requires a separate EPROM programmer and UV eraser for design iteration. This part is now considered legacy and is typically sourced through distributors stocking remaining inventory.
Drop-in alternatives for EP910IPC-50 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910IPC-50 (same form factor and footprint) — differing in Package, Technology, Mounting Type, Operating Temperature, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910IPC-25
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EP910IPC-15
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EP910IPC-12
✅ Drop-In✓ In Stock
$14.2 / Unit
View Datasheet →EP910ILC-50
✅ Drop-In✓ In Stock
$10.85 / Unit
View Datasheet →EP910ILC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP910ILI-25
✅ Drop-In✓ In Stock
$7.25 / Unit
View Datasheet →EP910IPC-50 Maximum Ratings & Electrical Characteristics
| Product Type | Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD |
| Propagation Delay (tPD) | 50 ns |
| Clock-to-Output (tCO) | 35 ns |
| User I/O Pins | 24 |
| Package | 40-pin Ceramic DIP (IPC, windowed) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | -40C to +85C (industrial) |
| Technology | CMOS EPROM cell |
| Programming Method | Off-board EPROM programmer + UV erase |
| Erasure Method | UV light through ceramic window (IPC package) |
| Mounting Type | Through-Hole (DIP) |
EP910IPC-50 Pin Configuration
| Pin 1 | I/O — User I/O pin (macrocell) |
| Pin 2 | I/O — User I/O pin (macrocell) |
| Pin 3 | I/O — User I/O pin (macrocell) |
| Pin 4 | I/O — User I/O pin (macrocell) |
| Pin 5 | I/O — User I/O pin (macrocell) |
| Pin 6 | I/O — User I/O pin (macrocell) |
| Pin 7 | I/O — User I/O pin (macrocell) |
| Pin 8 | I/O — User I/O pin (macrocell) |
| Pin 9 | I/O — User I/O pin (macrocell) |
| Pin 10 | I/O — User I/O pin (macrocell) |
| Pin 11 | I/O — User I/O pin (macrocell) |
| Pin 12 | I/O — User I/O pin (macrocell) |
| Pin 13 | I/O — User I/O pin (macrocell) |
| Pin 14 | I/O — User I/O pin (macrocell) |
| Pin 15 | I/O — User I/O pin (macrocell) |
| Pin 16 | I/O — User I/O pin (macrocell) |
| Pin 17 | I/O — User I/O pin (macrocell) |
| Pin 18 | I/O — User I/O pin (macrocell) |
| Pin 19 | I/O — User I/O pin (macrocell) |
| Pin 20 | I/O — User I/O pin (macrocell) |
| Pin 21 | I/O — User I/O pin (macrocell) |
| Pin 22 | I/O — User I/O pin (macrocell) |
| Pin 23 | I/O — User I/O pin (macrocell) |
| Pin 24 | I/O — User I/O pin (macrocell) |
| Pin 25 | GND — Ground |
| Pin 26 | VCC — 5V power supply |
| Pin 27 | NC — Not connected (per datasheet) |
| Pin 28 | NC — Not connected (per datasheet) |
| Pin 29 | NC — Not connected (per datasheet) |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | NC — Not connected (per datasheet) |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | NC — Not connected (per datasheet) |
| Pin 35 | NC — Not connected (per datasheet) |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
Typical Applications
EP910IPC-50 is suitable for 6 applications: Legacy Microprocessor Bus Decoding, Replacement of Discrete TTL/CMOS Glue Logic, Industrial State-Machine and Sequencer Logic, Educational and Prototyping Platforms, Vintage Computer and Retro-Computing Restoration, Avionics and Military Legacy Systems.
Legacy Microprocessor Bus Decoding
The EP910IPC-50 is well suited to legacy microprocessor bus-decoding applications where address and control signals must be combined into chip-select or enable outputs. With 24 user I/O pins and 50ns tPD, the part can decode 16-bit or 20-bit address buses and generate multiple chip-selects in a single device. Compared to discrete 74LS/74HC glue logic, a single EP910IPC-50 replaces 6-10 SSI/MSI packages, reducing board area and propagation skew. Designers should budget the 50ns tPD against the processor's access-time window; for 8 MHz 8086/6809 designs the part is comfortably within timing margins, but for 16/25 MHz systems a -25 or -15 speed grade is recommended.
Recommended
Replacement of Discrete TTL/CMOS Glue Logic
The EP910IPC-50 is ideal for consolidating scattered TTL/CMOS glue logic into a single programmable device, reducing component count and improving reliability. A typical 74LS138 + 74LS08 + 74LS374 + 74LS245 cluster (4-6 ICs) can be absorbed into one EP910IPC-50 with spare macrocells available for additional decoding. The 5V single-supply operation matches legacy TTL rails directly, eliminating level-shifters. Design verification should confirm worst-case tPD + tCO against the system clock period; the -50 grade is appropriate for systems clocked up to ~10 MHz, beyond which the faster EP910IPC-25 is preferred.
Recommended
Industrial State-Machine and Sequencer Logic
The EP910IPC-50 fits industrial controller state-machine designs requiring deterministic timing, registered outputs, and -40C to +85C industrial temperature operation. Its sum-of-products architecture supports both combinatorial and registered logic with separate macrocell flip-flops, enabling Moore and Mealy machines in a single device. The 50ns tPD suits step-rate sequencing in motor-control, valve-driver, and conveyor logic running at typical step frequencies of 1-5 kHz. Designers should confirm UV-erase compatibility if iterative prototyping is expected - the IPC windowed ceramic package supports unlimited erase/reprogram cycles.
Recommended
Educational and Prototyping Platforms
The EP910IPC-50's UV-erasable windowed ceramic DIP package makes it a strong choice for educational labs and prototyping platforms where students iteratively program, test, erase, and reprogram logic designs. The 40-pin DIP format is breadboard-friendly and through-hole-solderable on standard perfboard, eliminating the need for SMD reflow equipment. The 50ns tPD is more than adequate for typical lab exercises (counters, decoders, simple state machines) and provides timing headroom that hides race conditions during student debugging. Universities teaching CPLD/FPGA history often pair the Classic EPLD with a modern MAX-series CPLD to illustrate the evolution of programmable logic.
Recommended
Vintage Computer and Retro-Computing Restoration
The EP910IPC-50 is highly relevant to vintage computer restoration projects from the late 1980s and early 1990s, where Altera Classic EPLDs were widely used in industrial PCs, S-100 bus systems, and early SCSI adapters. Replacement of failed originals with exact-speed-grade parts preserves original system timing characteristics. The 5V single supply and 24 I/Os match the bus-interface requirements of vintage 8086/80286/68000 systems. Restoration engineers often prefer exact tPD grades rather than faster parts to maintain timing compatibility with adjacent vintage ICs whose timing margins were designed around the 50ns grade.
Recommended
Avionics and Military Legacy Systems
The EP910IPC-50's ceramic DIP (IPC) package and Altera Classic EPLD pedigree make it valuable for maintaining legacy avionics and military systems where the original bill of materials specified ceramic-windowed EPLDs for UV-reprogrammability and radiation tolerance. Parts in the IPC and DM (883B) packages were MIL-STD-883 screened variants for harsh-environment applications. While the -50 speed grade is rarely the bottleneck in legacy avionics, the package format and pinout must match exactly. For new military designs, modern MAX V CPLDs are recommended, but EP910-class parts remain in service for legacy sustainment programs.
Recommended
Recommended Products Summary
Engineering reference data for EP910IPC-50 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910IPC-25 | EP910IPC-15 | EP910IPC-12 | EP910ILC-50 | EP910ILC-25 | EP910ILI-25 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 40-pin Ceramic DIP (IPC) | 40-pin Ceramic DIP (IPC) - same | 40-pin Ceramic DIP (IPC) - same | 40-pin Ceramic DIP (IPC) - same | 44-pin Ceramic JLCC (ILC) - different footprint | 44-pin Ceramic JLCC (ILC) - different footprint | 44-pin Ceramic JLCC (ILI) - different footprint |
| Propagation Delay (tPD) | 50 ns | 25 ns (-50%, faster) | 15 ns (-70%, faster) | 12 ns (-76%, faster) | 50 ns (same) | 25 ns (-50%, faster) | 25 ns (-50%, faster) |
| User I/O Pins | 24 | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 24 (same) | 24 (same) |
| Supply Voltage | 4.75V to 5.25V (5V) | 4.75V to 5.25V (5V) | 4.75V to 5.25V (5V) | 4.75V to 5.25V (5V) | 4.75V to 5.25V (5V) | 4.75V to 5.25V (5V) | 4.75V to 5.25V (5V) |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM (UV-erasable) - same | CMOS EPROM (UV-erasable) - same | CMOS EPROM (UV-erasable) - same | CMOS EPROM (UV-erasable) - same | CMOS EPROM (UV-erasable) - same | CMOS EPROM (UV-erasable) - same |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C (industrial -40 to +85) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Slowest speed grade in the EP910 Classic EPLD family (vs EP910IPC-25)
- Through-hole ceramic DIP package versus JLCC surface-mount (vs EP910ILC-50)
- UV-erasable EPROM cell technology (vs EP910PC-25 (plastic OTP variant))
Design Notes
The EP910IPC-50 is a UV-erasable EPROM-based EPLD, not in-system programmable. Any design change requires removing the part from the PCB, erasing it under a UV lamp for 20+ minutes, and reprogramming with an external EPROM programmer. Plan design iterations accordingly and keep at least one or two spare pre-programmed parts if field replacement is expected. Designers migrating to modern designs should consider a MAX V or MAX 10 CPLD with JTAG in-system programmability to eliminate the erase cycle entirely.
At 50ns tPD, the EP910IPC-50 is suitable for systems with clock frequencies up to roughly 10 MHz when used as registered logic, and up to roughly 15 MHz for purely asynchronous combinatorial decoding. For bus decoding in 8086/80286 systems (5-10 MHz) the -50 grade has adequate margin; for 80386 or 68030 systems (16-25 MHz) designers should specify the EP910IPC-25 or faster. Always budget worst-case tPD + tCO + setup against the system clock period to avoid setup-time violations.
The 40-pin ceramic DIP (IPC) is a through-hole package with 0.600 inch (15.24 mm) row spacing and standard 0.100 inch (2.54 mm) pin pitch. Provide standard DIP-40 through-hole pads with adequate annular ring for hand-soldering or wave-solder assembly. Decouple VCC (pin 26) with a 0.1uF ceramic capacitor placed within 5 mm of the pin, plus a bulk 10uF tantalum or electrolytic on the same 5V rail. Connect all GND pins to a low-impedance ground plane - the part has multiple GND connections that should all be tied to the same ground reference.
Compliance Information
RoHS, REACH, lead-free, and halogen-free status were not stated in the verified web data and are marked unknown. Ceramic DIP packages of this vintage commonly contain lead-bearing terminations and may not meet RoHS as currently specified. AEC-Q100 is not applicable - this is a programmable logic device, not an automotive-qualified analog IC. Confirm all compliance status with the distributor's material declaration before use in regulated designs.
