EP910IPC-15 vs EP910PC-25 Comparison
Detailed side-by-side comparison of EP910IPC-15 by Altera and EP910PC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-15 | EP910PC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $16.92 |
| Device Family | Altera Classic EPLD (EP910 series) | β |
| Product Type | Erasable Programmable Logic Device (EPLD) | β |
| Architecture | PAL-type, CMOS | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 10 |
| I/O Pins | 24 | β |
| Product Terms | 240 | β |
| External Clocks | 2 | β |
| Propagation Delay (tPD) | 15 ns | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V +/- 10% |
| Operating Temperature | 0C to +70C (commercial, IPC suffix) | 0C to +70C (commercial) |
| Package | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (Plastic DIP) |
| Mounting Type | Through-Hole | β |
| Process Technology | CMOS | β |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | β |
| Pin Count | 40 | 24 |
| RoHS Status | [DATA_NEEDED: rohs status not confirmed in verified data] | β |
| Product Family | β | Classic EPLD |
| Usable Gates | β | 900 |
| Integration Gates (typical) | β | 4800 |
| Pin-to-Pin Delay (tPD) | β | 25 ns |
| Maximum Operating Frequency (fMAX) | β | 33.3 MHz |
| Technology | β | CMOS EPROM |
| Dedicated I/O Pins | β | 12 |
| TTL Compatibility | β | 100% TTL emulation |
| Erasure Method | β | Not erasable in plastic package (windowless) |